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MISSING LINK ELECTRONICS

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Missing Link Electronics (MLE) is a Silicon-Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets. MLE's mission is to develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open-Source software for dependable, configurable embedded system platforms. MLE's solution for Intel comprise of mixed-signal FPGA technology, a direct and single-chip integration of analog I/Os, such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) into an Intel® FPGA. MLE supports Intel® FPGA customers to realize video and imaging processing systems, such as wireless transmitters for 3G-SDI full-HD video streaming. MLE also actively contributes to the Nios-II ecosystem.

Missing Link Electronics (MLE) is a Silicon-Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets. MLE's mission is to develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open-Source software for dependable, configurable embedded system platforms. MLE's solution for Intel comprise of mixed-signal FPGA technology, a direct and single-chip integration of analog I/Os, such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) into an Intel® FPGA. MLE supports Intel® FPGA customers to realize video and imaging processing systems, such as wireless transmitters for 3G-SDI full-HD video streaming. MLE also actively contributes to the Nios-II ecosystem.

Address

Industriestr. 10
Neu-Ulm, Bayern, 89231
Germany

Regional Coverage

Americas :

North America Region

Europe, Middle East, and Africa :

Central Eastern Europe

Central European Region

Northern European Union Region

Southern European Union Region

Western European Union Region

People's Republic of China :

People's Republic of China

Use Cases

High Performance Computing

Others

Storage

Industry

Defense and Space

Communications :

Telecommunications

Health and Life Sciences :

Medical Imaging

Manufacturing :

Automotive

Company Resources

Offerings

Offering

Image for 1G-100G TSN Industrial Ethernet and Multiple Protocol Tunneling in One Cable for Virtual PLC - MLE FPGA IP Core Design

1G-100G TSN Industrial Ethernet and Multiple Protocol Tunneling in One Cable for Virtual PLC - MLE FPGA IP Core Design

MLE’s Robo/TSN IP can tunnel modern multi-Gig sensor data (GigEVision, PCIe, MIPI CSI-2, GMSL, …) as well as industrial protocols like Ethercat or Profinet , and is scalable from 1 to 100 Gbps to connect sensors and actuators from automation cells to AI engines and/or virtualized/software PLCs in edge cloud data centers via high-speed TSN.

by MISSING LINK ELECTRONICS

Offering

Image for 200G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

200G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

MLE 200G NVMe FPGA RAID can transfer bulky data from multiple sensors to a RAID of NVMe SSDs at speeds 200 Gbps. It implements a channel-based architecture, supports data-in-motion pre- and post-processing and is highly scalable with regards to bandwidth and recording capacity. Multiple systems can further be cascaded via high-accuracy IEEE time-synchronization for faster or deeper recording. Adaptable signal front-ends support many different I/O standards in a “mix & match” fashion. It is also compatible with Linux Software-RAID (via the Linux MD driver), allowing recording at high data rates and replaying at slower speeds, or vice versa.

by MISSING LINK ELECTRONICS

Offering

Image for 400G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

400G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

MLE 400G NVMe FPGA RAID can transfer bulky data from multiple sensors to a RAID of NVMe SSDs at speeds up to 400 Gbps. It implements a channel-based architecture, supports data-in-motion pre- and post-processing and is highly scalable with regards to bandwidth and recording capacity. Multiple systems can further be cascaded via high-accuracy IEEE time-synchronization for faster or deeper recording. Adaptable signal front-ends support many different I/O standards in a “mix & match” fashion. It is also compatible with Linux Software-RAID (via the Linux MD driver), allowing recording at high data rates and replaying at slower speeds, or vice versa.

by MISSING LINK ELECTRONICS

Offering

Image for 100G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

100G NVMe FPGA RAID High Speed Data Recording and Replay - MLE FPGA Design

MLE 100G NVMe FPGA RAID can transfer bulky data from multiple sensors to a RAID of NVMe SSDs at speeds 100 Gbps. It implements a channel-based architecture, supports data-in-motion pre- and post-processing and is highly scalable with regards to bandwidth and recording capacity. Multiple systems can further be cascaded via high-accuracy IEEE time-synchronization for faster or deeper recording. Adaptable signal front-ends support many different I/O standards in a “mix & match” fashion. It is also compatible with Linux Software-RAID (via the Linux MD driver), allowing recording at high data rates and replaying at slower speeds, or vice versa.

by MISSING LINK ELECTRONICS

Offering

Image for Intel® FPGA Design Services / IP Design Services - MLE

Intel® FPGA Design Services / IP Design Services - MLE

Intel® FPGAs offer a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built-in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power, and cost.

by MISSING LINK ELECTRONICS

Offering

Image for 100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

Image for 40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

Image for 50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

Image for 50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 50G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

Image for Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

by MISSING LINK ELECTRONICS

Offering

Image for 100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

Image for Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design

Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design

MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.

by MISSING LINK ELECTRONICS

Offering

Image for 40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

Image for 10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

Image for 10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS