GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.2. Generating the Design

Configure the SDI II Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design examples.
Figure 3. Generating the Design Flow
  1. Create an empty project targeting Agilex™ 5 device family and select the desired device.
  2. In the IP Catalog, locate and double-click GTS SDI II Intel® FPGA IP . The IP Parameter Editor window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
  4. Click OK. The parameter editor appears.
  5. On the IP main tab, select your desired IP settings. The generated design example is based on your settings.
  6. In the SDI_II wrapper 3 option, select Both Base and PHY option for integrated PHY design or BASE only option for separate PHY design.
  7. On the IP Analog Parameters tab, select your desired analog parameter settings. The generated design example is based on your settings.
    Note: The RX Adaptation mode option in the IP Analog Parameters tab is fixed to manual as SDI does not support auto adaptation.
  8. On the Design Example tab, select the desired parameter for the design example. Select Simulation to generate the testbench.
  9. To generate the design example with DS groups: In the IP main tab, select Both Base and PHY option. In the Design Example tab, select the Enable Dual Simplex Generation option.
  10. Select Simulation to generate the testbench and select Synthesis to generate the hardware design example.
  11. For Target Development Kit, select the relevant FPGA development kit. You may change the target device using the Change Target Device parameter if your board revision does not match the grade of the default targeted device.
  12. Click Generate Example Design button to initiate the design generation.
Figure 4. Design Example Tab in SDI II IP Parameter Editor
3 SDI_II wrapper option allows you to generate design with SDI II IP cores with the PHY directly integrated when you choose Both BASE and PHY. If you choose BASE only, you can change the transceiver setting in PHY IP based on your needs.
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