2.3.2.1. Clocking Scheme Components
| Diagram Label | Description |
|---|---|
| TX PLL refclock 4 | TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be a free running clock.
|
| RX CDR refclock 4 |
Transceiver clock data recovery (CDR) reference clock, of any frequency divisible by the transceiver for that data rate. Only a single reference clock frequency which the recommendation is 148.5 MHz is required to support both integer and fractional frame rate. It must be a free running clock.
Note: Do not share the TX PLL reference clock with the RX transceiver reference clock for parallel loopback design. In parallel loopback designs, the TX PLL clock is tuned to match the RX recovered clock frequency.
|
| SysPLL refclock | GTS System PLL reference clock, of any frequency divisible by System PLL for that output frequency. It must be a free running clock connected from a dedicated transceiver reference clock pin to the input clock port of GTS System PLL Clocks Intel® FPGA IP |
| GPIO clock / RX coreclk / DR clocks | SDI RX core reference clock which must be a free running clock depending on the RX core clock Frequency parameter value. All generated design examples have this clock set to 148.5 MHz regardless of the GUI option because of the development kit's default limited clock frequency option. |
| TX/RX transceiver clkout2 | Recovered clock from transceiver. For SD video standard:
For HD video standard:
For 3G/6G/12G video standard:
|
| TX/RX transceiver clkout | This is the div2 clock from System PLL output clock which the GTS PMA/FEC Direct PHY Intel® FPGA IP is operating in. This clock must be connected to a DCFIFO which serves as the interface between SDI II IP and the Direct PHY IP. |
Note: Altera recommends not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design since TX PLL clock is going to be tuned to match RX recovered clock frequency.
4 Intel recommends you not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design because TX PLL clock is going to be tuned to match RX recovered clock frequency.