GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.3. Functional Description

Figure 7. Parallel Loopback with Simplex Mode IP Core (SDI_II wrapper = BASE only, Enable Dual Simplex Generation = 0)

For the above parallel loopback design, the transceiver is located outside of GTS SDI II IP. The transceiver is instantiated at the TX/RX top level module. For this mode, you have the option to change the transceiver settings based on your needs. PMA Direct PHY TX and RX is separated into Simplex IP.

This variant is for designs with:
  • Nextera daughter card with separate channel for TX and RX.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 8. Serial with Simplex Mode IP Core (SDI_II wrapper = BASE only, Enable Dual Simplex Generation = 1)

For the above serial design, the transceiver is located outside of GTS SDI II IP. The transceiver is instantiated at the DS Groups module. For this mode, you have the option to change the transceiver settings based on your needs. PMA Direct PHY TX and RX is separated into Simplex IP.

This variant is for designs with:
  • FMC loopback card.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 9. Parallel Loopback with Simplex Mode IP Core (SDI_II wrapper = Both BASE and PHY, Enable Dual Simplex Generation = 0)

For the above parallel loopback design, the transceiver is located inside of GTS SDI II IP. The transceiver is instantiated at the SDI TX/RX module (IP wrapper). GTS SDI II IP (TX and RX) is separated into Simplex IP.

This variant is for designs with:
  • Nextera daughter card with separate channel for TX and RX.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 10. Parallel Loopback with Simplex Mode IP Core (SDI_II wrapper = Both BASE and PHY, Enable Dual Simplex Generation = 1)

For the above parallel loopback design, the transceiver is located inside the DS Groups. The transceiver is instantiated at the DS Groups module. SDI II IP (TX and RX) is wrapped in the Dual Simplex group. Both RX and TX transceivers are placed at the same channel.

This variant is for designs with:
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 11. Serial with Simplex Mode IP Core (SDI_II wrapper = Both BASE and PHY, Enable Dual Simplex Generation = 1)

For the above serial design, the transceiver is located inside the DS Groups. The transceiver is instantiated at the DS Groups module. SDI II IP (TX and RX) is wrapped in the Dual Simplex group. Both RX and TX transceivers are placed at the same channel.

This variant is for designs with:
  • FMC loopback card.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.

Section Content
Design Components
Clocking Scheme

Level Two Title