GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
1. GTS SDI II Intel® FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.4. Design Example Parameters

Table 3.  Design Example Tab Parameters
Parameter Value Description
Select Design
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback

Select a design example for generation.

  • Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
  • Parallel loopback without external VCXO: Parallel loopback design utilizes internal PLL on Intel® FPGA IP to synchronize the clock between RX and TX. The TX PLL operates in fractional mode with 141 MHz as its reference clock frequency.
  • Serial loopback: An internal video pattern generator generates along with TX and transmits to RX. This design allows simple demonstration when you do not have a video source available.
Enable Dual Simplex Generation On

Turn on this option to generate dual simplex necessary files for Quartus® Prime compilation.

This option is enabled by default when you select Serial Loopback in the Select Design parameter option. If you select Parallel loopback with external VCXO, you can choose to enable or disable this option. This option is not available for Parallel loopback without external VCXO.

Note: You need to select Both BASE and PHY option in the SDI_II wrapper parameter in the IP parameter tab for this option to be available for Parallel loopback with external VCXO. Otherwise, this option is not available for this design.
Simulation On / Off Turn on this option to generate necessary files for simulation testbench.
Synthesis On

Turn on this option to generate necessary files for Quartus® Prime compilation and hardware demo.

Generate File Format
  • Verilog
  • VHDL
 Select the HDL format for generated design example fileset. Note that the HDL format only affects the generated top level IP files. All the other files, for example testbenches and top level files for hardware demo are in Verilog.
Select Daughter Card
  • Nextera VIDIO 12G-SDI FMC card
 Select the daughter card for the targeted design example.
Select Board
  • No Development Kit
  • Agilex™ 5 I-Series SOC Development Kit
  • Custom Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.
  • Agilex™ 5 I-Series SOC Development Kit: This option automatically selects the project's target device to match the device on this development kit. You can change the target device with the Change Target Device parameter if your board revision has a different grade from the default targeted device. All the pins assignment is set accordingly to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA device. You may need to set the pin assignment yourself.
Change Target Device On / Off

Turn on to select different device grade for Altera development kit.

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