AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

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ID 817911
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Interfaces 5. Parameters 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features
4. Interfaces x
4.1. System Block Diagram 4.2. Clocks 4.3. Resets 4.4. PCIe IP-facing Interfaces 4.5. User-facing Interfaces
4.4. PCIe IP-facing Interfaces x
4.4.1. PCIe AXI-ST TX Interface (ss_tx_st) 4.4.2. PCIe AXI-ST RX Interface (ss_rx_st) 4.4.3. Control and Status Register Interface (ss_csr_lite) 4.4.4. Flow Control Credit Interface 4.4.5. Configuration Intercept Interface (CII) 4.4.6. Completion Timeout Interface (ss_cplto) 4.4.7. Function Level Reset Interface 4.4.8. Control Shadow Interface (ss_ctrlshadow)
4.4.4. Flow Control Credit Interface x
4.4.4.1. Transmit Flow Credit Interface (ss_txcrdt) 4.4.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
4.4.5. Configuration Intercept Interface (CII) x
4.4.5.1. Configuration Intercept Request Interface (ss_cii_req) 4.4.5.2. Configuration Intercept Response Interface (ss_cii_resp)
4.4.7. Function Level Reset Interface x
4.4.7.1. FLR Received Interface (ss_flrrcvd) 4.4.7.2. FLR Completion Interface (ss_flrcmpl)
4.5. User-facing Interfaces x
4.5.1. H2D AXI-ST Source (h2d_st_initatr) 4.5.2. D2H AXI-ST Sink (d2h_st_respndr) 4.5.3. BAM AXI-MM Master (bam_mm_initatr) 4.5.4. BAS AXI-MM Slave (bas_mm_respndr) 4.5.5. PIO AXI-Lite Master (pio_lite_initiatr) 4.5.6. HIP Reconfig AXI-Lite Slave (user_csr_lite) 4.5.7. User Event MSI-X (user_msix) 4.5.8. User Event MSI (user_msi) 4.5.9. User Function Level Reset (user_flr) 4.5.10. User Configuration Intercept Interface - EP Only 4.5.11. Configuration Slave (cs_lite_respndr) - RP Only
4.5.10. User Configuration Intercept Interface - EP Only x
4.5.10.1. User Configuration Intercept Request Interface (user_cii_req) 4.5.10.2. User Configuration Intercept Response Interface (user_cii_resp)
5. Parameters x
5.1. IP Settings 5.2. PCIe Settings 5.3. Design Examples
5.2. PCIe Settings x
5.2.1. MCDMA Settings 5.2.2. PCI Express / PCI Capabilities 5.2.3. Base Address Registers
5.2.1. MCDMA Settings x
5.2.1.1. Multichannel DMA Mode 5.2.1.2. Bursting Master Mode 5.2.1.3. Bursting Slave Mode 5.2.1.4. BAM+BAS Mode 5.2.1.5. BAM+MCDMA Mode 5.2.1.6. BAM+BAS+MCDMA Mode
5.2.2. PCI Express / PCI Capabilities x
5.2.2.1. PCIe Device 5.2.2.2. PCIe MSI-X
5.2.2.2. PCIe MSI-X x
5.2.2.2.1. PCIe PF MSI-X 5.2.2.2.2. PCIe VF MSI-X
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Interfaces
5. Parameters
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

4.5.4. BAS AXI-MM Slave (bas_mm_respndr)

The AXI-MM Bursting Slave module translates AXI-MM Read address channel and Write address channel transactions from the user logic to PCI Express Mrd and Mwr TLPs respectively. The returned PCI Express CplD packets are translated to AXI-MM Read Data channel interface as a response to the AXI-MM read address channel transaction.

Interface Clock: axi_mm_clk

DWIDTH:
  • 1024 bits for Gen5 1x16
  • 512 bits for Gen5 2x8, Gen4 1x16, Gen3 1x16
  • 256 bits for Gen4 2x8, Gen3 2x8
Table 27.  BAS AXI-MM Slave Interface
Signal Name Direction Description
Write Address Channel
bas_axi_mm_awvalid Input

Write address valid.

This signal indicates that the channel is signaling valid write address and control information.

bas_axi_mm_awready Output

Write address ready.

This signal indicates that the slave is ready to accept an address and associated control signals.

bas_axi_mm_awid[3:0] Input

Write address ID. This signal is the identification tag for the write address group of signals.

bas_axi_mm_awaddr[63:0] Input

Write address.

The write address gives the address of the first transfer in a write burst transaction.

The Bursting Slave’s addresses must be aligned to the width of the data bus. For example, if the data width is 64B, the addresses must align to 64B.

bas_axi_mm_awuser[15:0] Input

Write Address User.

The write address user information encodes the following information:
  • EP mode: User-defined signal - {1'b0, vf_num[11:0], vf_active, pf_num[2:0]}
  • RP mode: User-defined signal - to be used as the Requester ID in the Memory Write TLPs.
bas_axi_mm_awlen[7:0] Input

Burst length.

The burst length gives the exact number of transfers in a burst.

This information determines the number of data transfers associated with the address.

bas_axi_mm_awsize[2:0] Input

Burst size.

This signal indicates the size of each transfer in the burst.

bas_axi_mm_awburst[1:0] Input

Burst type.

The burst type and the size information, determine how the address for each transfer within the burst is calculated.

Only INCR burst type is supported.

bas_axi_mm_awlock Input Lock type.

Tied to '0'.
bas_axi_mm_awuser[15:0] Input

Root Port mode: User-defined signal - to be used as the Requester ID in the TLPs.

Endpoint mode: User-defined signal - {vf_num[11:0], vf_active, pf_num[2:0]}.

bas_axi_mm_awprot[2:0] Input

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Write Data Channel
bas_axi_mm_wvalid Input

Write Data Valid
bas_axi_mm_wready Output

Write Data Ready

Indicates the receiver can accept write data
bas_axi_mm_wdata[DWIDTH-1:0] Input

Write Data
bas_axi_mm_wstrb[DWIDTH/8-1:0] Input

Write Strobes
bas_axi_mm_wlast Input

Write Last
Write Response Channel
bas_axi_mm_bvalid Output

Write Response Valid
bas_axi_mm_bready Input

Write Response Ready
bas_axi_mm_bid[3:0] Output

Response ID.

This signal is the identification tag of the write response.

bas_axi_mm_bresp[1:0] Output

Write Response
Read Address Channel
bas_axi_mm_arvalid Input

Read address valid.

This signal indicates that the channel is signaling valid read address and control information.

bas_axi_mm_arready Output

Read address ready.

This signal indicates that the slave is ready to accept an address and associated control signals

bas_axi_mm_arid[3:0] Input

Read address ID.

This signal is the identification tag for the read address group of signals.

bas_axi_mm_araddr[63:0] Input

Read address.

The read address gives the address of the first transfer in a read burst transaction.

The Bursting Slave’s addresses must be aligned to the width of the data bus. For example, if the data width is 64B, the addresses must align to 64B.

bas_axi_mm_aruser[15:0] Input Read address user.
The read address user signal encodes the following information:
  • EP mode: User-defined signal - {1'b0, vf_num[11:0], vf_active, pf_num[2:0]}
  • RP mode: User-defined signal - to be used as the Requester ID in the Memory Read TLPs.
bas_axi_mm_arlen[7:0] Input

Burst length.

The burst length gives the exact number of transfers in a burst.

bas_axi_mm_arsize[2:0] Input

Burst size.

This signal indicates the size of each transfer in the burst.

bas_axi_mm_arburst[1:0] Input

Burst type.

The burst type and the size information, determine how the address for each transfer within the burst is calculated.

Only INCR burst type is supported.
bas_axi_mm_arlock Input

Lock type.

Tied to '0'.
bas_axi_mm_aruser[15:0] Input User-defined signal - {vf_num[11:0], vf_active, pf_num[2:0]}
bas_axi_mm_arprot[2:0] Input

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Read Data Channel
bas_axi_mm_rvalid Output

Read data valid.

This signal indicates that the channel is signaling the required read data.

bas_axi_mm_rready Input

Read data ready.

This signal indicates that the master can accept the read data and response information.

bas_axi_mm_rid[3:0] Output

Read ID tag.

This signal is the identification tag for the read data group of signals generated by the slave.

bas_axi_mm_rdata[DWIDTH-1:0] Output

Read Data
bas_axi_mm_rresp[1:0] Output

Read response.

This signal indicates the status of the read transfer. EXOKAY is not supported on Agilex™ 7 FPGAs.

bas_axi_mm_rlast Output

Read last.

This signal indicates the last transfer in a read burst.
Level Two Title