GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 817713
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSim* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.8. Running the Design Example x
2.8.1. Running the PIO Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A. Appendix

2.2. Generating the Design Example

Figure 5. Procedure to Generate Design Example
Figure 6. Example Designs Tab
  1. In the Quartus® Prime Pro Edition software, create a new project (File ➤ New Project Wizard).
  2. Specify the Directory, Name and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Family, Device & Board Settings under Family, select Agilex 5.
  5. Select the Target Device for your design.
  6. Click Next.
  7. For Add Files click Finish.
  8. In the IP Catalog, locate and add the GTS AXI Streaming Intel FPGA IP for PCI Express.
  9. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  10. On the System Settings tabs, specify the parameters for your IP variation.
  11. On the Example Designs tab, make the following selections:
    • For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the design example generation time.
    • For Generated HDL Format, both Verilog and VHDL are supported in the current release.
    • For Currently Selected Example Design, only PIO is supported in this release.
    • For Target Development Kit, select either the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (ES1) or NONE to target the device selected for your current Quartus® Prime software project. If you select the development kit, the settings including the pin assignments are included in the .qsf file of the generated design example, and you are not required to add them manually. These settings are board-specific for the development kit.
    Note: When the PCIe* Hard IP mode is set to Gen4 x4 Interface 256 bit or Gen4 x2/x1 Interface 128 bit, do not select Agilex 5 FPGA E-Series 065B Modular Development Kit (ES1) as the Target Development Kit to avoid compilation errors.
  12. Select Generate Example Design to create a design example that you can simulate and download to hardware. When the prompt asks you to specify the directory for your design example, you can accept the default directory, /intel_pcie_gts_0_example_design , or choose another directory.
  13. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
Level Two Title