GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSim* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.8. Running the Design Example x
2.8.1. Running the PIO Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A. Appendix

A.1.5. ebfm_cfgwr_imm_wait Procedure

The ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configuration register. This procedure waits until the write completion has been returned.

Location

Syntax

ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num, regb_ad, regb_ln, imm_data, compl_status)

Arguments

bus_num

PCI Express bus number of the target device.

dev_num

PCI Express device number of the target device.

fnc_num

Function number in the target device to be accessed.

regb_ad

Byte-specific address of the register to be written.

regb_ln

Length, in bytes, of the data written. Maximum length is four bytes. The regb_ln and the regb_ad arguments cannot cross a DWORD boundary.

imm_data

Data to be written.

This argument is reg[31:0].

The bits written depend on the length:

  • 4: 31 down to 0
  • 3: 23 down to 0
  • 2: 15 down to 0
  • 1: 7 down to 0
compl_status

This argument is reg[2:0].

This argument is the completion status as specified in the PCI Express specification. The following encodings are defined:

  • 3’b000: SC— Successful completion
  • 3’b001: UR— Unsupported Request
  • 3’b010: CRS — Configuration Request Retry Status
  • 3’b100: CA — Completer Abort
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