GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

ID 817660
Date 4/07/2025
Public
Document Table of Contents

5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP

Each non- PCIe* IP has one reference clock buffer failed status port o_refclk_bus_out to indicate the status of the reference clock for that side of the device. For multiple IP applications, only one port needs to be connected to the GTS Reset Sequencer Intel® FPGA IP. You can choose which IP is connected GTS Reset Sequencer Intel® FPGA IP and leave the rest unconnected.

From the GTS Reset Sequencer Intel® FPGA IP, there is one output port, o_shoreline_refclk_fail_stat, that you must connect to your logic to monitor the status of the reference clock buffer. The example connections are shown in the following figure:
Figure 84. Reference Clock Buffer Status Connection