Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.5. ECC Engine Functionality

The NAND Flash controller has an ECC engine logic that allows the detection and correction of multiple errors in the data stream read from the NAND Flash device. The ECC check bits are inserted in the data stream after each transferred ECC sector. The NAND Flash controller supports nominal sector sizes of 1024 and 2048 bytes. For write operations, the transferred user data enters into the ECC encoder and after a data block size matches the ECC sector size, the ECC checksum bytes are injected into the data stream and both the user data and the checksum are written into the flash device in contiguous areas in the NAND page. For read operations, one block of data the data from the flash device enters into the ECC decoder (user data + checksum) and error check and corrections are performed (if number of errors is less than the correction capability). After the correction, the user data is transferred to the host interface for data processing. The NAND Flash page organization that this controller uses can be observed in the figure in the Data Layout section.

The correction capability defines the size of the ECC checksum required. The correction strength can be configured with corr_str field in the ecc_config_0 (0x0428) register. The ECC engine is capable of protecting up to 40 additional bytes than the nominal sector size. This means that we can protect additional data with the same number of bytes required for the checksum. This additional data typically could be used as metadata that is used to track the state of a page or a block in the Flash device (commonly stored in the last sector). The following table describes the number of check-bit bytes for a specific correction capability and sector size. This also shows the encoded value to be used in the corr_str field in the register mentioned earlier.

Table 207.  ECC Correction Capability Encoding
Correction Capability (Bits) Sector Size (Bytes) Check-bit Size (Bytes) Encoded value for corr_str
8 1024 - 1064 16 0
2048 - 2088
16 1024 - 1064 30 1
2048 - 2088
32 1024 - 1064 60 2
2048 - 2088
64 1024 - 1064 120 3
2048 - 2088
72 1024 - 1064 136 4
2048 - 2088
96 1024 - 1064 180 5
2048 - 2088
130 1024 - 1064 242 6
2048 - 2088

The sector size is determined by the value of the transfer_cfg_1 (0x0404) register. The sector sizes in this register only should include any user data and metadata, but you need to consider that the number of bytes to protect should be inside of the range defined in the table above and all the ECC checksum bytes, user data, metadata, CRC bytes and padding bytes should fit in a NAND Flash device page (normally the total page size defines the correction capability).

Note: Because of the algorithm proprieties used the ECC engine, this guarantees the correction ability up to 128 bits.