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5.3.6.3.2. Data Layout
The data to be stored in the NAND Flash device is organized in pages and the NAND Flash controller needs to know the number of data bytes that can be stored in a page.
When using NAND Flash devices, the data to be stored is normally protected with ECC data so it is possible to validate and correct any possible error introduced in the data. With the introduction of ECC protection, there is also the concept of sectors, which are data sets with certain sizes for which the ECC is calculated (see ECC Engine Functionality). Besides the ECC protection, adding CRC checksum protection to the data is also supported by the NAND Flash controller. In addition, ECC and CRC data are stored in the NAND Flash device as part of the content of a page.
The NAND Flash controller uses the size of the sectors and number of sectors to calculate the page size as shown in the following table.
Parameter | Register | Description |
---|---|---|
sector_cnt | transfer_cfg_0 (0x0400) | Number of sectors per single NAND Flash page. |
sector_size | transfer_cfg_1 (0x0404) | Size of all sectors except the last one in bytes. |
last_sector_size | transfer_cfg_1 (0x0404) | Size of the last sector in bytes. The last sector size may be different from the rest as it is common to store additional data in this sector (also referred to as metadata). |
The page size is calculated using the following formula:
page_size = (sector_cnt - 1) * sector_size + last_sector_size
If adding CRC data is enabled, this adds an additional 8 bytes to the data stream which is also processed by the BCH engine when creating ECC data. This decreases the space that could be allocated for the metadata space by 8 bytes.
Factor in checksum of CRC and ECC check data when setting the sizes of sectors, so the overall data size does not exceed the real page size in the NAND Flash device (do not add them to the sector_cnt and last_sector_cnt parameter values, but they need to be considered to determine if they fit in the real page in the NAND device under the ECC restrictions).
The figure below shows the following:
- On the left side: Page layout of NAND data in host memory where it is just the raw data to be stored in the Flash device. This layout is used as reference to determine the values for the sector size parameters.
- On the right side: Additional bytes that are added when CRC and ECC are enabled.
The NAND device page layout that the NAND controller uses is shown in the following figure. Although it is common that ECC data is placed in the spare area of the page, the NAND controller actually handles the full page (main area + spare area) as a single memory space. The diagram also shows the space in the page assigned to keep the factory bad block mark which is typically located at the beginning of the spare region. The NAND controller supports a mechanism that allows automatically skipping access to this region, therefore preventing erasing this (see ECC Engine section).
You must also consider that each of the sectors in the NAND page must be aligned to 8-byte boundaries. In the case when the number of transmitted data bytes for a single sector does not meet this requirement, you must add padding bytes. This is shown in the following figure.