Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Embedded Memory Overview 2. Agilex™ 5 Embedded Memory Architecture and Features 3. Agilex™ 5 Embedded Memory Design Considerations 4. Agilex™ 5 Embedded Memory IP References 5. Agilex™ 5 Embedded Memory Debugging 6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Embedded Memory Overview x
1.1. Agilex™ 5 Embedded Memory Features
2. Agilex™ 5 Embedded Memory Architecture and Features x
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Agilex™ 5 Embedded Memory Clocking Modes 2.6. Agilex™ 5 Embedded Memory Configurations 2.7. Force-to-Zero 2.8. Coherent Read Memory 2.9. Freeze Logic 2.10. True Dual Port Dual Clock Emulator 2.11. Initial Value of Read and Write Address Registers 2.12. Timing/Power Optimization Feature in M20K Blocks
2.1. Byte Enable in Agilex™ 5 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.5. Agilex™ 5 Embedded Memory Clocking Modes x
2.5.1. Single Clock Mode 2.5.2. Read/Write Clock Mode 2.5.3. Input/Output Clock Mode 2.5.4. Asynchronous/Synchronous Clears in Clocking Modes 2.5.5. Output Read Data in Simultaneous Read/Write 2.5.6. Independent Clock Enables in Clocking Modes
2.6. Agilex™ 5 Embedded Memory Configurations x
2.6.1. Mixed-Width Port Configurations
2.8. Coherent Read Memory x
2.8.1. Forwarding Logic
3. Agilex™ 5 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 5 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. FIFO Intel® FPGA IP 4.3. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. FIFO Intel® FPGA IP x
4.2.1. Release Information for FIFO Intel® FPGA IP 4.2.2. Configuration Methods 4.2.3. Specifications 4.2.4. FIFO Functional Timing Requirements 4.2.5. SCFIFO ALMOST_EMPTY Functional Timing 4.2.6. FIFO Output Status Flag and Latency 4.2.7. FIFO Metastability Protection and Related Options 4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.2.9. SCFIFO and DCFIFO Show-Ahead Mode 4.2.10. Different Input and Output Width 4.2.11. DCFIFO Timing Constraint Setting 4.2.12. Coding Example for Manual Instantiation 4.2.13. Instantiation Template 4.2.14. Design Example 4.2.15. Gray-Code Counter Transfer at the Clock Domain Crossing 4.2.16. Guidelines for Embedded Memory ECC Feature 4.2.17. FIFO Intel® FPGA IP Parameters 4.2.18. Reset Scheme
4.2.3. Specifications x
4.2.3.1. Verilog HDL Prototype 4.2.3.2. VHDL Component Declaration 4.2.3.3. VHDL LIBRARY-USE Declaration 4.2.3.4. HDL Code from Parameterizable Macros Template 4.2.3.5. FIFO Signals 4.2.3.6. FIFO Parameter Settings
4.2.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.2.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.2.11. DCFIFO Timing Constraint Setting x
4.2.11.1. Embedded Timing Constraint 4.2.11.2. User Configurable Timing Constraint
4.2.11.2. User Configurable Timing Constraint x
4.2.11.2.1. SDC Commands
4.3. Shift Register (RAM-based) Intel® FPGA IP x
4.3.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.3.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.3.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.3.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.3.5. Shift Register Ports and Parameters Setting
1. Agilex™ 5 Embedded Memory Overview
2. Agilex™ 5 Embedded Memory Architecture and Features
3. Agilex™ 5 Embedded Memory Design Considerations
4. Agilex™ 5 Embedded Memory IP References
5. Agilex™ 5 Embedded Memory Debugging
6. Document Revision History for the Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs

1.1. Agilex™ 5 Embedded Memory Features

The Agilex™ 5 devices contain the following types of memory blocks: M20K blocks, and memory logic array blocks (MLABs).
  • 20-kilobit (Kb) M20K blocks
    • Blocks of dedicated memory resources.
    • Ideal for larger memory arrays, while providing a large number of independent ports.
  • 640-bit MLABs
    • Memory blocks configured from dual-purpose logic array blocks (LABs).
    • Ideal for wide and shallow memory arrays.
    • Optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
    • Each MLAB is made up of ten adaptive logic modules (ALMs).

In Agilex™ 5 devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Agilex™ 5 devices provide one 32×20 simple dual-port SRAM block per MLAB.

The Agilex™ 5 embedded memory blocks support the following operation modes:
  • Single-port
  • Simple dual-port
  • True dual-port
  • Simple quad-port
  • ROM
Table 1.   Agilex™ 5 Embedded Memory FeaturesThis table summarizes the features supported by the Agilex™ 5 embedded memory blocks.
Features M20K MLAB
Maximum operating frequency
  • 1 GHz (simple dual-port RAM mode)
  • 600 MHz (true dual-port and simple quad-port RAM mode)

850 MHz
Total RAM bits (including parity bits) 20,480 bits 640 bits
Byte enable Supported Supported
Address clock enable

(address stall)

 Supported (only in simple dual-port RAM mode) Supported
Simple dual-port mixed width Supported N/A
FIFO buffer mixed width Supported N/A
Memory Initialization File (.mif) Supported Supported
Dual-clock mode Supported (only in simple dual-port RAM mode) Supported
Full synchronous memory Supported Supported
Asynchronous memory N/A Only for flow-through read memory operations
Power-up state Output ports are cleared
  • Registered output ports are cleared
  • Unregistered output ports read memory contents
Asynchronous/Synchronous Clears
  • Output registers and output latches
  • Supports asynchronous clear on read address registers (only in simple dual-port and simple quad-port modes)
 Output registers and output latches
Write/read operation triggering Rising clock edges Rising clock edges
Same-port read-during-write
  • Single Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to New Data
  • Simple Quad Port: Output ports set to Don't Care
Output ports set to Don't Care
Mixed-port read-during-write
  • Simple Dual Port RAM: Output ports set to Old Data or Don't Care
  • True Dual Port RAM: Output ports set to Don't Care
  • Simple Quad Port: Output ports set to new_a_old_b
Output ports set to New Data, Old Data, or Don't Care
Error Correction Code (ECC) support
  • Built-in support ×32-wide simple dual-port mode
  • Parity bits

N/A
Force-to-Zero Supported N/A
Coherent read memory Supported N/A
Freeze logic Supported N/A
True dual port (TDP) dual clock emulator Supported N/A
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