Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813773
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 Configuration Details 3. Agilex™ 5 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Agilex™ 5 Configuration Features 7. Agilex™ 5 Debugging Guide 8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs x
1.1. Agilex™ 5 Configuration Overview 1.2. Agilex™ 5 Configuration Architecture
1.1. Agilex™ 5 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Agilex™ 5 Devices
1.2. Agilex™ 5 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Updating the SDM Firmware 1.2.1.2. Specifying Boot Order for Agilex™ 5 SoC Devices
2. Agilex™ 5 Configuration Details x
2.1. Agilex™ 5 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and GTS Transceivers 2.5. Agilex™ 5 Configuration Pins 2.6. Configuration Clocks 2.7. Generating Compressed .sof File
2.5. Agilex™ 5 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. I/O Standards and Features for Configuration Pins 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.5.3.3. I/O Standards and Features for Configuration Pins x
2.5.3.3.1. IBIS Model
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Agilex™ 5 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II) x
3.1.7.1. Functional Description 3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration 3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP 3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP 3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP 3.1.7.6. Supported Flash Memory Devices
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration x
3.1.7.2.1. Parallel Flash Loader II Intel® FPGA IP Parameters 3.1.7.2.2. Parallel Flash Loader II Intel® FPGA IP Signals
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP 3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address 3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration 3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins 3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
3.2.5. Skew Tolerance Guidelines x
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Embedded Memory Block Initial Conditions 4.5.3. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Agilex™ 5 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Agilex™ 5 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Agilex™ 5 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. Understanding and Troubleshooting Configuration Pin Behavior 7.8. Configuration Debugger Tool
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

5.6.5. Adding an Application Image

Complete the following steps to add an application image to flash memory:

  1. Set up exclusive access to the AS x4 interface and flash memory by running the QSPI_OPEN and QSPI_SET_CS commands in the Tcl Console window. You now have exclusive access to the AS x4 interface and flash until you relinquish access by running the QSPI_CLOSE command. Write the new application image to the flash memory using the QSPI_WRITE command.
  2. Alternatively, the rsu1.tcl script includes the program_flash function that programs a new application image into flash memory. The following command accomplishes this task: 
    program_flash new_application_image.rpd 0x03FF0000 1024

    The program_flash function takes three arguments:

    1. The .rpd file to write to flash memory.
    2. The start address.
    3. Number of words to write for each QSPI_WRITE command. The QSPI_WRITE supports up to 1024 words per write instruction.

    Figure 85. Program New Application Image 
    $ source rsu1.tcl
/channels/local/top/master_1
$ program_flash new_application_image.rpd 0x03ff0000 1024
total number of words is 584704
total number of page is 571
total number of sector is 36
reading rpd is completed
start writing flash
writing flash is completed
  3. Write the new application image start address to a new image pointer entry in the configuration firmware pointer block (CPB) using the QSPI_WRITE command. Ensure that the new image pointer entry value is 0xFFFFFFFF before initiating the write.
    Note: When using HPS to manage RSU, you must update both copies of the Configuration Pointer Block (CPB0 and CPB1) and the sub-partition table (SPT). In a non-HPS case, while updates to both copies of the pointer blocks are mandatory, the updates to the sub-partition table are not required. For more details about the SPT and CPB, refer to Sub-partition Table Layout for the sub-partition table layout and Pointer Block Layout for the pointer block layout.
Based on the example described above, the address offset 0x20 in the CPB0 and CPB1 must point to the start address of the application image. The next new image pointer entry value must be 0xFFFFFFFF before you write the start address of the new application image to the next image pointer entry.
Table 54.  Configuration Firmware Pointer Block Contents
CPB Start Address + 0x20 Content Value
CPB0 + 0x20 = 0x004A0020 Current application image pointer entry (highest priority) 0x004B0000
CPB0 + 0x28 = 0x004A0028 Next image pointer entry 0xFFFFFFFF
CPB1 + 0x20 = 0x004A8020 Current application image pointer entry (highest priority) 0x004B0000
CPB1 + 0x28 = 0x002EC028 Next image pointer entry 0xFFFFFFFF
You can use the QSPI_read function verify that the new image pointer entry value is 0xFFFFFFFF . The QSPI_read function takes in two arguments:
  1. Start address
  2. Number of words to read

Figure 86. Verifying that the New Image Pointer entry Value is 0xFFFFFFFF 
$ qspi_read 0x004a0020 1
0x004b0000
$ qspi_read 0x004a0028 1
0xffffffff
% qspi_read 0x004a8020 1
0x004b0000
% qspi_read 0x004a8028 1
0xffffffff
You can now proceed to write the new application image address to next image entry by using the QSPI_write_one_word function. The QSPI_write_one_word function takes in two arguments:
  1. Address
  2. The value of the word
Figure 87. Writing an Address Pointer to the New Image Pointer Entry 
% qspi_write_one_word 0x004a0028 0x03FF0000
% qspi_write_one_word 0x004a8028 0x03FF0000

You can now do a QSPI_read function to the next image pointer entry to ensure that it is written with the start address of the desired new application image.

Figure 88. Verifying the Update to the New Image Pointer 
% qspi_read 0x004a0028 1
0x03FF0000
% qspi_read 0x004a8028 1
0x03FF0000

Host software can now reconfigure the Agilex™ 5 FPGA with the new application image by asserting the nCONFIG pin. Alternatively, you can power cycle the PCB. After reconfiguration, check the current image address. The expected address is 0x03ff0000. After adding a new image, your application image list includes the newly added application image and the old application image, which is now a secondary image. The newly added application image has the highest priority.

Note: When the remote system update host loads an application image, the decision firmware traverses the image pointer entries in reverse order. The new image has the highest priority when you restart the device.
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