Visible to Intel only — GUID: jnf1697092279897
Ixiasoft
Visible to Intel only — GUID: jnf1697092279897
Ixiasoft
7.3.1. AXI4-Stream Receive (RX) Interface
The packet received from the link is presented to application logic on this interface. The interface supports data width of 16 bytes (128 bits), 32 bytes (256 bits), and 64 bytes (512 bits). The TLP header, BAR, function number of TLP, and prefix signals are sent in line with data.
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
p<n>_ss_app_st_rx_tvalid | Output | p<n>_axi_st_clk | Indicates that the remote transmit interface is driving a valid transfer. |
p<n>_app_ss_st_rx_tready | Input | p<n>_axi_st_clk | Indicates that the receive interface can accept a transfer in the current cycle. |
p<n>_ss_app_st_rx_tdata[(a-1):0] 1 | Output | p<n>_axi_st_clk | Data bus used to provide the data that is passing across the interface. |
p<n>_ss_app_st_rx_tkeep[(a/8-1):0] 1 | Output | p<n>_axi_st_clk | A byte qualifier used to indicate whether the content of the associated byte is valid. The invalid bytes are allowed only during ss_app_st_tx_tlast cycle. The sparse ss_app_st_tx_tkeep is not allowed. |
p<n>_ss_app_st_rx_tlast | Output | p<n>_axi_st_clk | Indicates end of data/command transmission. |
p<n>_app_ss_st_rx_tuser_halt[2:0] | Input | p<n>_axi_st_clk | Indicates that the user logic wants to temporarily halt reception of a particular type of packet.
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The timing diagrams in the following sections are for the simple packing scheme.
The following figure shows a timing diagram for command with data. The completion, memory write, messages, and the configuration write commands fall under the command with data category.
The first command transfers a payload of 64 Bytes. The receive interface is ready to accept a command at clock cycle 1 but the transmit interface does not have any command to transfer in that same cycle. The transmit interface starts the transfer in the next cycle.
The second command transfers a payload of 128 Bytes. Here, the receive interface is not ready to accept a command when the transmit interface has asserted valid. The transmit interface holds the information on the bus until it observes ready from the receive interface.
The following figure shows a timing diagram for command with data followed by command without data. The completion, memory write, messages, and the configuration write commands fall under command with data category. The memory read, configuration read, messages without data, and completion without data fall under command without data category.
The first command transfers a payload of 64 Bytes. The receive interface is ready to accept a command at clock cycle 1 but the transmit interface does not have any command to transfer in that same cycle. The transmit interface starts the transfer in the next cycle.
The second command is a command without data. Here, the receive interface is not ready to accept a command when the transmit interface has asserted valid. The transmit interface holds the information on the bus until it observes ready from the receive interface.
The first command transfers the payload of 67 Bytes.
The second command is a command without data.