Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813663
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 5. Interface Signals 6. Configuration Registers 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. TX Promiscuous (Transparent) Mode 3.4.8. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Avalon® Memory-Mapped Interface Programming Signals 5.5. Avalon® Streaming Data Interfaces 5.6. Avalon® Streaming Flow Control Signals 5.7. Avalon® Streaming Status Interface 5.8. PHY-side Interfaces 5.9. IEEE 1588v2 Interfaces
5.5. Avalon® Streaming Data Interfaces x
5.5.1. Avalon® Streaming TX Data Interface Signals 5.5.2. Avalon® Streaming RX Data Interface Signals 5.5.3. Avalon® Streaming Data Interface Clocks
5.7. Avalon® Streaming Status Interface x
5.7.1. Avalon® Streaming Interface TX Status Signals 5.7.2. Avalon® Streaming Interface RX Status Signals
5.8. PHY-side Interfaces x
5.8.1. XGMII TX Signals 5.8.2. XGMII RX Signals 5.8.3. GMII TX Signals 5.8.4. GMII RX Signals 5.8.5. Clock Enable Signals
5.9. IEEE 1588v2 Interfaces x
5.9.1. IEEE 1588v2 Egress TX Signals 5.9.2. IEEE 1588v2 Ingress RX Signals 5.9.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. RX Configuration and Status Registers 6.8. ECC Registers 6.9. Statistics Registers 6.10. Timestamp Registers
6.10. Timestamp Registers x
6.10.1. Calculating PHY Total Latency 6.10.2. Calculating Deterministic Latency 6.10.3. PTP Register Configuration
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.7.2. Avalon® Streaming Interface RX Status Signals

Table 23.   Avalon® Streaming Interface RX Status Signals
Signal Direction Width Description
avalon_st_rxstatus_valid Out 1

When asserted, this signal qualifies the avalon_st_rxstatus_data[] and avalon_st_rxstatus_error[] signals. The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted.

avalon_st_rxstatus_data[] Out 40

Contains information about the RX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame. Ignore this bit when the MAC is configured not to detect stacked VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 33: When set to 1, indicates a VLAN frame. Ignore this bit when the MAC is configured not to detect VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[] Out 7

When set to 1, the respective bit indicates the following error type in the RX frame.

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: CRC error.
  • Bit 4: Unused.
  • Bit 5: Unused.
  • Bit 6: PHY error.

The IP core presents the error status on this bus in the same clock cycle it asserts the avalon_st_rxstatus_valid signal. The error status is invalid when an overflow occurs.

avalon_st_rx_pfc_status_valid Out 1

When asserted, this signal qualifies the avalon_st_rx_pfc_status_data[] signal. This signal applies only to 10G operating mode.

avalon_st_rx_pfc_status_data[] Out n

(4 - 16)

n = 2 x Number of PFC queues parameter

When set to 1, the respective bit indicates the flow control request from the remote partner, for example:

  • Bit 0: XON request for priority queue 0.
  • Bit 1: XOFF request for priority queue 0.
  • Bit 2: XON request for priority queue 1.
  • Bit 3: XOFF request for priority queue 1.
  • Bit 4: XON request for priority queue 2.
  • Bit 5: XOFF request for priority queue 2.

When a pair of bits (Example: Bit 0 and Bit 1, Bit 3 and Bit 4, etc.) is set to 0, the respective bit indicates there is no flow control frame sent.

This signal applies only to 10G operating mode.

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