Visible to Intel only — GUID: skr1683105710748
Ixiasoft
Visible to Intel only — GUID: skr1683105710748
Ixiasoft
1.3. Memory Blocks
- M20K blocks
- Memory logic array blocks (MLABs)
The M20K blocks support ECC. The ECC feature detects and corrects data errors at the output of the memory.
Item | M20K Block |
---|---|
Built-in support | In ×32-wide simple dual-port mode |
Features | 32-bit word error detection and correction:
The ECC cannot guarantee detection or correction of non-adjacent two-bit (or more) errors. |
Flags indicating memory status |
The status flags are part of the regular outputs from the memory block. |
When you engage ECC, the M20K memory runs slower than in non-ECC simple dual-port mode. To achieve a higher performance, enable the optional ECC pipeline registers before the output decoder. Note that this adds one cycle of latency.
For more information about implementing ECC with the embedded memory Intel® FPGA IPs, refer to Embedded Memory User Guide: Agilex™ 5 FPGAs and SoCs.