SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Agilex™ 5 SEU Mitigation Implementation Guides 5. IP and Software References 6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets 2.7. Retrieving SEU Statistics using Mailbox Command
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Agilex™ 5 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Performing External Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Predefined Safe Locations 4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 4.6.6. Injecting Errors to Random Locations 4.6.7. Injecting Errors to Specific Locations 4.6.8. Injecting Double Adjacent Errors 4.6.9. Injecting SDM ECC Errors
4.6.4. Injecting Errors to Predefined Safe Locations x
4.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 4.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 4.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 4.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
4.6.8. Injecting Double Adjacent Errors x
4.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.9. Injecting SDM ECC Errors x
4.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 4.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 4.6.9.4. Injecting SDM ECC Errors: Mailbox Command
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 5 SEU Mitigation Implementation Guides
5. IP and Software References
6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

3.2. SmartVID Error Message Bits

The SmartVID error message bits store the error message when the Agilex™ 5 detects an error in the external voltage regulator.

The SmartVID error message contains information about the type of error and the specific error details. You can retrieve the contents of the error message from the generic_sdm_data_out signal of the Advanced SEU Detection Intel® FPGA IP.

Table 10.  SmartVID Error Message Bits Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in generic_sdm_data_out signal

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error type:
  • 0000—SEU Error
  • 0001—SDM and subsystem ECC error
  • 0010—miscellaneous CNT error 4
  • 0011—SmartVID error
  • 0100—miscellaneous SDM error
  • 0101—External Memory Interface
  • Remaining values—reserved
3:0 Reserved

Error data

(Least significant 32-bit word in generic_sdm_data_out signal)

32 31:29 SmartVID error type:
  • 000—fault or warning not listed in the following types (general error)
  • 001—communication, memory, or logic fault
  • 010—temperature fault or warning
  • 011—input undervoltage fault
  • 100—output overcurrent fault
  • 101—output overvoltage fault
  • 110—no power to the output of the voltage regulator fault, including the voltage regulator not being enabled
  • 111—device busy and unable to respond
28 Correction status:
  • 0—not corrected
27:12 Reserved
11:0 Specific SmartVID error type 000 details:
  • 12'd0—no error
  • 12'd1—NACK on PMBus address
  • 12'd2—NACK on PMBus command
  • 12'd3—NACK on PMBus data or payload
  • 12'd4—NACK on PMBus general call
  • 12'd5—NACK on PMBus general read
  • 12'd6—NACK on PMBus slave abort lost
  • 12'd7—NACK on PMBus master abort lost
  • 12'd8—FPGA user abort error
  • 12'd9—PWRMGT_SDA signal stuck low
  • Remaining values—reserved
Note: When a SmartVID error occurs, Altera recommends that you check the integrity of the SmartVID signals and the voltage regulator on board.
4 Contact Intel Premier Support and quote ID #15015577051 for further assistance when you see this error.
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