SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Agilex™ 5 SEU Mitigation Implementation Guides 5. IP and Software References 6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets 2.7. Retrieving SEU Statistics using Mailbox Command
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Agilex™ 5 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Performing External Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Predefined Safe Locations 4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 4.6.6. Injecting Errors to Random Locations 4.6.7. Injecting Errors to Specific Locations 4.6.8. Injecting Double Adjacent Errors 4.6.9. Injecting SDM ECC Errors
4.6.4. Injecting Errors to Predefined Safe Locations x
4.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 4.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 4.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 4.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
4.6.8. Injecting Double Adjacent Errors x
4.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.9. Injecting SDM ECC Errors x
4.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 4.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 4.6.9.4. Injecting SDM ECC Errors: Mailbox Command
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 5 SEU Mitigation Implementation Guides
5. IP and Software References
6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

4.5.2. Looking up the Sensitivity Map Header

Use the Advanced SEU Detection Intel® FPGA IP to perform .smh lookups.
Before you begin, ensure that you have turned on the Enable error detection check and Generate SEU sensitivity map file (.smh) options while setting up the SEU mitigation features.
To look up the Agilex™ 5 sensitivity map header, follow these steps:
  1. Read the .smh file header for the generic .smh information: 
    Address = 0
Word 0  = SMH_signature
Word 1  = (reserved, region_mask_size)
Word 2  = sector_info_base_address
  2. Read the three 32-bit words of sector information entry for:
    • Sector encoding scheme 32-bit address
    • Sector .smh data 32-bits address
    • 8 bits of sector .smh tag size (can be 1, 2, 4, or 8 bits)
    • 16 bits of ASD region map size that is the number of ASD region bit masks used by sector
    Address = sector_info_base_address + (sector_index*3)
Word 0  = encoding_scheme_address
Word 1  = sector_data_address
Word 2  = (reserved, regions_map_size, smh_tag_size)
  3. Read the following sector encoding scheme information for error location frame index and bit position within the frame:
    • Read the first three words of sector encoding scheme header information to obtain the encoding scheme parameters.
      Address = encoding_scheme_address
Word 0  = (reserved, frame_encoding_map_size)
Word 1  = frame_info_base_offset
Word 2  = frame_encoding_base_offset
    • Read the 32-bit frame information string for the frame number.
      Address = encoding_scheme_address + frame_info_base_offset + frame_index
Word 0  = (frame_encoding_index, frame_data_offset)
    • Get the 16-bit index into frame sensitivity data for a bit position.
      int16* frame_encoding_map = encoding_scheme_address
                            + frame_encoding_base_offset
                            + (frame_encoding_map_size 
                            * frame_encoding_index) / 4;
int16 tag_index           = frame_encoding_map[bit_position];
  4. Read the following data from the sector .smh data to establish the affected ASD regions:
    • The smh_tag_size bit length .smh tag for frame_data_offset and tag_index from step 2.
      int8* frame_data  = (sector_data_address + 1 
                    + (regions_map_size * region_mask_size + 31) / 32
                    + frame_data_offset*smh_tag_size);
int8 sensitivity_byte = frame_data[tag_index * smh_tag_size / 8];
int8 smh_tag      = (sensitivity_byte >> (tag_index * smh_tag_size % 8))
                    & ((0x1 << smh_tag_size) - 1);
    • A zero smh_tag indicates that the bit error location is not critical for any region. A non-zero tag indicates an index in the region map. To get a region mask for the smh_tag:
      int32* region_masks      = sector_data_address + 1;
int32 region_mask_offset = (smh_tag - 1) * region_mask_size;
int32 region_mask_word   = region_masks[region_mask_offset / 32];
int32 region_mask        = (region_mask_word >> region_mask_offset % 32)
                           & ((0x1 << (region_mask_size) - 1);

Section Content
Sensitivity Map Header Revision 4 File Format Reference

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