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4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Predefined Safe Locations
4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types
4.6.6. Injecting Errors to Random Locations
4.6.7. Injecting Errors to Specific Locations
4.6.8. Injecting Double Adjacent Errors
4.6.9. Injecting SDM ECC Errors
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2.4.1. Advanced SEU Detection Intel® FPGA IP
The Advanced SEU Detection Intel® FPGA IP allows you to perform on-chip and off-chip processing for SEU errors.
- On-chip—the soft IP provides error location reporting and lookup.
- Off-chip—an external unit such as a microprocessor performs error location lookup using information from the error message queue.
The Advanced SEU Detection IP does the following:
- Communicates with the secure device manager (SDM) to detect SEU event by sending commands and receiving responses for SEU error reports.
- Reads sensitivity map header (.smh) file to allow on-chip or off-chip lookup sensitivity processing, and reports criticality of SEU error occurrence in device based on the specified regions in the file.
Note: You cannot simulate the Advanced SEU Detection IP because the IP receives the response from SDM. To validate this IP core, Altera recommends that you perform hardware evaluation.