Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813159
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 FPGAs LAB and ALM Overview 2. Hyperflex® Register 3. Agilex™ 5 LAB and ALM Architecture and Features 4. Document Revision History for the Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs
3. Agilex™ 5 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Agilex™ 5 FPGAs LAB and ALM Overview
2. Hyperflex® Register
3. Agilex™ 5 LAB and ALM Architecture and Features
4. Document Revision History for the Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs

3.1.4. LAB Control Signals

There are two clock sources in each LAB control block, which generate two LAB clocks (LABCLK[1:0]) and two delayed LAB clocks (LABCLK_Phi1[1:0]) to drive the ALM registers and Hyper-Registers in the LAB. The LAB supports two unique clock enable signals and additional clear signals for the ALM registers.

The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. A low skew clock network distributes global signals to the row clocks [5..0]. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for routing efficiency. The Quartus® Prime Compiler automatically routes critical design paths on faster interconnects to improve design performance and optimizes the device resources.


Section Content
Clear Logic Control

Level Two Title