Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs

ID 813159
Date 4/01/2024
Public

3.1.4.1. Clear Logic Control

LAB-wide signals control the logic for the clear signal of the ALM register. The ALM register directly supports both a synchronous and an asynchronous clear. Each LAB supports one synchronous clear signal and two asynchronous clear signals.

Figure 5.  Agilex™ 5 LAB-Wide Control Signals