Logic Array Blocks and Adaptive Logic Modules User Guide: Agilex™ 5 FPGAs and SoCs

ID 813159
Date 4/01/2024
Public

3.2.3.3. Arithmetic Mode

The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to perform pre-adder logic. Therefore, each adder can add the output of two 4-input functions.

Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, and synchronous clear.

The clear and clock enable options are LAB-wide signals that affect all registers in the LAB. You can individually disable or enable these signals for each pair of registers in an adaptive LUT (ALUT). The Quartus® Prime software automatically places any registers that are not used by the counter into other LABs.

Figure 12.  Agilex™ 5 ALM in Arithmetic Mode