Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP Release Notes

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Date 7/08/2024
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1. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP Release Notes
1. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP Release Notes x
1.1. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP v2.0.1 1.2. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP v2.0.0 1.3. Intel Agilex® 7 F-Series and I-Series FPGA Memory Subsystem IP v1.0.1 1.4. Intel Agilex® 7 F-Series and I-Series FPGA Memory Subsystem IP v1.0.0
1. Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP Release Notes

1.4. Intel Agilex® 7 F-Series and I-Series FPGA Memory Subsystem IP v1.0.0

Table 10.  v1.0.0 2023.10.02
Quartus® Prime Version Description Impact
23.3 Verified in the Quartus® Prime software v23.3. Provides memory subsystem IP for use with Intel Agilex® 7 F-Series and I-Series FPGAs. The tables that follow summarize feature support.
Note: This documentation is preliminary and subject to change.
Table 11.  Memory Subsystem IP Feature Support Summary
Category Feature
Subsystem Number of physical interfaces 0 to 8
Number of user AXI-MM interfaces 0 to 8
Number of supported lookup IPs 0 to 4
External Memory Interface IP Support

For related information, refer to External Memory Interfaces Intel Agilex® 7 F and I-Series FPGA IP Release Notes

Memory protocol DDR4
DDR4 for HPS
Memory format Component
UDIMM
RDIMM
SODIMM
LRDIMM
Memory device speed grade DDR4 up to 3200 Mbps
Interface width <=72
Memory-Specific Adaptor Bank spreading optimization Yes
Conversion of user requests to burst-oriented requests Yes
Auto-precharge request generation Yes
Buffering Yes
Write copies Yes
Basic scheduling between read and write requests Yes
CAM IP Configured as BCAM Number of BCAM instances 0 – 4
Configuration interface AXI-Lite
Lookup request interface AXI-ST
Memory On-chip
Lookup algorithm Exact-match cuckoo filter
Management operations Lookup
Insert
Delete
Modify
Flush
Key width 16 to 512 bits
Number of entries 32 to 4196
Result width 8 to 1024 bits
CAM IP Configured as TCAM Number of TCAM instances 0 to 4
Number of core tables per TCAM instance 1 to 4
Configuration interface AXI-Lite
Lookup request interface AXI-ST
Memory On-chip
Lookup algorithm Ternary match
Management operations Lookup
Insert
Delete
Flush
Key width 16 to 512 bits
Number of entries 32 to 1024
Result width 8 to 1024 bits
CAM IP Configured as Multi-bin Lookup (MBL) IP Number of MBL instances 0 to 4
Number of logical tables per MBL instance 1 to 3
Configuration interface AXI-Lite
Lookup request interface AXI-ST
Memory External
Lookup algorithm Exact match
Management operations Lookup
Insert
Delete
Modify
Flush
Key width Up to 1280
Result width Up to 1280
Simulator Support (Verilog) VCS Yes
VCS-MX Yes
ModelSim Yes
Questa Yes
Xcelium Yes
Riviera No
Table 12.  Known Issues
Category Issue
BCAM Using key width greater than 265 may cause collisions.
TCAM The TCAM design example is not supported when Return highest match entry is disabled.
Level Two Title