Intel® Simics® Simulator for Intel® FPGAs: User Guide

Download PDF
ID 784383
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

5.4.2.1. Listing Processors

You can use processor-status command to check the condition of the target system’s CPUs. 

# Intel Simics simulator CLI

# Show the enabled/disabled status of all processors in the Intel Simics # simulation session.
simics> processor-status
-------------------------------------------
Processor	                     Status
-------------------------------------------
system.....agilex_hps.core[2]      disabled
system.....agilex_hps.core[3]      disabled
system.....agilex_hps.core[0]      enabled
system.....agilex_hps.core[1]      disabled
-------------------------------------------

In multicore architectures (as the example above), it is possible that more than one CPU gets enabled and is running. During the simulation, the Intel® Simics® simulator uses the enabled CPUs to control how the simulation advances in time (see Intel Simics Simulator Timing). To control this, Intel® Simics® uses the concept of “Selected front ended processor” that indicates which CPU is the one that owns the simulation control. The Intel® Simics® simulator switches the selection of this processor during the simulation. The selected front-ended processor is used in many global commands by default when no other CPU is specified in the command (this is shown in examples later in this document). You can use the psel command to determine which is the current frontend processor selected and you can also use this same command to switch to a different processor, as shown in the following capture: 

# Intel Simics simulator CLI 
simics> psel "system.board.fpga.soc_inst.hps_subsys.agilex_hpse.core[0]" 
simics> psel system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[1]
Setting new inspection object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[1]
simics> psel "system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[1]"

To list processors on the target system, enter list-processors command in the Intel® Simics® simulation console. This command shows the information about the state of each processor core to help diagnose the current state of the system. There are multiple switches available. Use help or tab-completion to see the available options. The -disassemble option indicates processor modes like wait states. 

list-processors [cell] [parent] ["class"] ["substr"] [-steps] [-cycles] [-time] [-pico-seconds] 
[-pc-va] [-pc-pa] [-disassemble] [-all]
Table 11.   list-processors Command Options
Command Description
-all Listing includes all "execute" objects, which includes objects which are either processors or clocks.

If any execute object is not scheduled by Intel® Simics® simulator itself (possibly scheduled indirectly by another object) an additional "Scheduled" column appears describing if the object is scheduled by Intel® Simics® simulator or not.

[cell] The cell prints only processors that belong to the specified cell.

The parent prints only processors underneath a certain component in the object hierarchy.

The class prints only processor objects of a specific class.

The substr argument prints only processors that have a certain string somewhere in the object hierarchy name.

A number of optional columns can be printed for each processor by using the following flags:

Table 12.   list-processors Command Options
Command Description
-steps Executed steps
-cycles Executed cycles
-time Executed time in seconds
-pico-seconds Executed time in picoseconds
-pc-va Virtual address program counter
-pc-pa Physical address program counter
-disassemble Current disassembly 
# Intel Simics simulator CLI  

simics> list-processors
-------------------------------------------------------
CPU Name                        CPU Class      Freq 
-------------------------------------------------------
system...agilex_hps.core[0]* arm-cortex-a55 400.00 MHz
system...agilex_hps.core[1]  arm-cortex-a55 400.00 MHz
system...agilex_hps.core[2]  arm-cortex-a76 400.00 MHz
system...agilex_hps.core[3]  arm-cortex-a76 400.00 MHz
-------------------------------------------------------
* = selected CPU

simics> list-processors -disassemble
-----------------------------------------------------------------------------
CPU Name                          CPU Class      Freq          Disassembly
-----------------------------------------------------------------------------
system...agilex_hps.core[0]* arm-cortex-a55 400.00 MHz  v:0x00000000fff67840
                                                        p:0x80000000fff67840 
                                                        str  w0, [x18, #332]
system...agilex_hps.core[1]  arm-cortex-a55 400.00 MHz  v:0x0000000000000000 
                                                        p:0x0000000000
                                                        Pending exception: 
                                                        ['Reset'], 
                                                        cpu is user disabled
system...agilex_hps.core[2]  arm-cortex-a76 400.00 MHz  v:0x0000000000000000 
                                                        p:0x0000000000
                                                        Pending exception: 
                                                        ['Reset'], 
                                                        cpu is user disabled
system...agilex_hps.core[3]  arm-cortex-a76 400.00 MHz  v:0x0000000000000000 
                                                        p:0x0000000000
                                                        Pending exception: 
                                                        ['Reset'], 
                                                        cpu is user disabled
-----------------------------------------------------------------------------
* = selected CPU

Notice in both examples in the above capture that the selected front-ended processor is being indicated with a *. You can use the processor path along with disassemble to inspect its information directly. 

# Intel Simics simulator CLI 
# Using processor.disassemble
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].disassemble
v:0xffff8000107dc170 p:0x80000000867dc170  ldrb w3, [x0, #185]

Similarly, the you can get the information of a processor using the [processor_path].info and the [processor_path].status commands. 

# Intel Simics simulator CLI 
# Checking information of processor system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0]
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].info
Information about system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] [class arm-cortex-a55]
===========================================================
         VMP status : Not Loaded
    JIT compilation : Enabled
    Clock frequency : 400 MHz
                CPI : 1.00
    Physical memory : system.board.fpga.soc_inst.hps_subsys.agilex_hps.cpu_mem[0]
               Cell : system.cell
# Checking the status of processor Core0

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].status
Status of system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] [class arm-cortex-a55]
===================================================
    Clock frequency : 400.000000 MHz
           Activity : Executing (fetch/execute from program counter)
             Cycles : 0
    Program counter : 0x00000000
    Instruction set : ARM
            Context : system.cell_context

You can also use list-objects namespace = [processor name] to inspect each of the processors. 

# Intel Simics simulator CLI  

# Inspect processor system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] 
simics> list-objects namespace=system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0]
----------------------------------------------------------------
Component Class             Object 
----------------------------------------------------------------
<vp_intel_agilex_5_soc>     hps (alias for system....agilex_hps)
----------------------------------------------------------------
---------------------------------------------------
 Class                         Object 
---------------------------------------------------
---------------------------------------------------

# Inspect the vtime object of processor core[0] 
simics> list-objects namespace=system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].vtime
------------------------------------------------------------
Component Class               Object
------------------------------------------------------------
<vp_intel_agilex_5_soc>  hps (alias for system...agilex_hps)
------------------------------------------------------------
-----------------------------------------------------------
 Class                         Object 
-----------------------------------------------------------
<cycle-counter>    system...agilex_hps.core[0].vtime.cycles
<ps-clock>         system...agilex_hps.core[0].vtime.p
-----------------------------------------------------------
Note: The examples presented in this section show the vtime object under the processor objects. This object is related to CPU virtual time. The objects under this object include CPU parameters, such as number of cycles executed or frequency. The information in these parameters can be different from the real CPU parameters values. To get the real value of these parameters, refer to the Intel Simics Simulator Timing section.
Level Two Title