Intel® Simics® Simulator for Intel® FPGAs: User Guide

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. Intel® Simics® Simulator and Virtual Platforms 3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio 4. Installing the Intel® Simics® Simulator for Intel® FPGAs 5. Getting Started with Intel® Simics® Simulator 6. Debugging Target Software 7. Networking with the Simulated Target System 8. Intel® Simics® Scripting 9. Software Debug Examples with Intel® Simics® Simulator 10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide A. Intel® Simics® Simulator Command Reference
1. About This Document x
1.1. Documentation Conventions for Examples 1.2. Terminology 1.3. List of Acronyms
2. Intel® Simics® Simulator and Virtual Platforms x
2.1. Device Model and Virtual Platforms 2.2. Intel® Simics® Simulator 2.3. Intel® Simics® Simulator Architecture
2.2. Intel® Simics® Simulator x
2.2.1. Intel® Simics® Simulator for Intel FPGAs Capabilities
4. Installing the Intel® Simics® Simulator for Intel® FPGAs x
4.1. Installing the Intel® Simics® Simulator for Intel® FPGAs on Linux* Systems 4.2. Installing the Intel® Simics® Simulator for Intel® FPGAs on Microsoft Windows* Systems 4.3. Installing Ashling* RiscFree* IDE for Intel® FPGAs 4.4. Intel® Simics® Simulator for Intel® FPGAs Support
5. Getting Started with Intel® Simics® Simulator x
5.1. Simulation Set Up 5.2. Starting the Simulation 5.3. Intel® Simics® Simulator Command-Line Interface (CLI) 5.4. Hardware Inspection 5.5. Intel® Simics® Simulator Timing
5.1. Simulation Set Up x
5.1.1. Initializing an Intel® Simics® Project and Deploying a Virtual Platform 5.1.2. Understanding Target Scripts
5.2. Starting the Simulation x
5.2.1. Starting a Simulation from a Command Prompt 5.2.2. Starting a Simulation with Ashling* RiscFree* IDE
5.3. Intel® Simics® Simulator Command-Line Interface (CLI) x
5.3.1. Version of the Intel® Simics® Simulator for Intel FPGAs Software 5.3.2. Simulation Run Control from CLI 5.3.3. Intel® Simics® Simulator Command Scope 5.3.4. Intel® Simics® Simulator CLI Variables and Operations 5.3.5. Intel® Simics® Simulator CLI Command Completion and Command History 5.3.6. Intel® Simics® Command-Line Interface Help 5.3.7. Capture of CLI Session to a File 5.3.8. Intel® Simics® Simulator File Location and Intel® Simics® Search Path
5.4. Hardware Inspection x
5.4.1. Listing Objects in the Target System 5.4.2. Processor (CPU) Inspection 5.4.3. Device Inspection 5.4.4. Memory Mapping and Memory Inspection 5.4.5. Logging
5.4.2. Processor (CPU) Inspection x
5.4.2.1. Listing Processors 5.4.2.2. Inspect Processor Registers
5.4.3. Device Inspection x
5.4.3.1. Retrieve List of Devices 5.4.3.2. Inspecting Device Registers
5.4.4. Memory Mapping and Memory Inspection x
5.4.4.1. Memory Mapping Inspection 5.4.4.2. Memory Inspection
5.4.5. Logging x
5.4.5.1. Breakpoints on CLI Log Messages
5.5. Intel® Simics® Simulator Timing x
5.5.1. CPU Frequency 5.5.2. CPU Cycles and Steps 5.5.3. Events 5.5.4. Enable Real Time
6. Debugging Target Software x
6.1. Intel® Simics® Debugger and Debug Context 6.2. Capturing Serial Console Output 6.3. Breakpoints 6.4. Debugging Target Software with Symbol Files 6.5. Debugging Target Software with Ashling* RiscFree* Debugger 6.6. Capturing CPU Instruction Execution Trace
6.3. Breakpoints x
6.3.1. Memory Breakpoints 6.3.2. Temporal Breakpoints 6.3.3. CPU Control Register Breakpoints 6.3.4. Hardware Access Breakpoints 6.3.5. CPU Register Breakpoints 6.3.6. Tracing Breakpoints 6.3.7. Text Console Activity Breakpoints
6.4. Debugging Target Software with Symbol Files x
6.4.1. Loading Symbol Files in a Simulation
6.5. Debugging Target Software with Ashling* RiscFree* Debugger x
6.5.1. Remote Debugging with RiscFree* IDE
6.5.1. Remote Debugging with RiscFree* IDE x
6.5.1.1. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on the Same System 6.5.1.2. Remote Debugging With Intel® Simics® Simulation and RiscFree* IDE on Different Systems 6.5.1.3. Remote Access to the Target System Serial Console
7. Networking with the Simulated Target System x
7.1. Network Simulation and Service Node 7.2. Connectivity Between Host PC and Target System
7.2. Connectivity Between Host PC and Target System x
7.2.1. Port Forwarding 7.2.2. Transferring Files Between Host PC and Target System 7.2.3. Accessing Target System from Host PC Through HTTP 7.2.4. Networking Commands Reference Table
7.2.1. Port Forwarding x
7.2.1.1. Incoming Port Forwarding 7.2.1.2. Outgoing Port Forwarding
7.2.1.1. Incoming Port Forwarding x
7.2.1.1.1. Example of an SSH Connection with Incoming Port Forwarding
7.2.1.2. Outgoing Port Forwarding x
7.2.1.2.1. Example of SSH Connection With Outgoing Port Forwarding 7.2.1.2.2. Example of SSH Connection via NAPT
7.2.2. Transferring Files Between Host PC and Target System x
7.2.2.1. Transferring Files with SCP service 7.2.2.2. Transferring Files with TFTP service
7.2.2.1. Transferring Files with SCP service x
7.2.2.1.1. Transferring Files With SCP Service via Forwarding Ports 7.2.2.1.2. Transferring Files with SCP from Target System to Host PC via NAPT
7.2.2.2. Transferring Files with TFTP service x
7.2.2.2.1. TFTP Using Forwarding Port 7.2.2.2.2. TFTP via NAPT 7.2.2.2.3. TFTP Using TFTP Server in Intel® Simics® Service Node
8. Intel® Simics® Scripting x
8.1. Scripts in CLI
8.1. Scripts in CLI x
8.1.1. Variables 8.1.2. Command Return Values 8.1.3. Control Flow Commands 8.1.4. Local Variables 8.1.5. Integer Conversion 8.1.6. Accessing Configuration Parameters 8.1.7. Error Handling in Scripts 8.1.8. Script Branches
8.1.8. Script Branches x
8.1.8.1. Script Branches Commands 8.1.8.2. Variables in Script Branches 8.1.8.3. Branch Synchronization 8.1.8.4. Canceling Script Branches 8.1.8.5. Script Branches Restrictions
9. Software Debug Examples with Intel® Simics® Simulator x
9.1. Debugging Linux* User-Mode Application
9.1. Debugging Linux* User-Mode Application x
9.1.1. Debugging a Linux Application with GDB 9.1.2. Debugging a Linux Application with RiscFree* IDE
9.1.1. Debugging a Linux Application with GDB x
9.1.1.1. Debugging with GDB Debug from Host PC Using Forwarding Ports 9.1.1.2. Debugging with GDB from Host PC with Intel® Simics® Simulator GDB Server
1. About This Document
2. Intel® Simics® Simulator and Virtual Platforms
3. Intel® Simics® Simulator for Intel® FPGAs Device Portfolio
4. Installing the Intel® Simics® Simulator for Intel® FPGAs
5. Getting Started with Intel® Simics® Simulator
6. Debugging Target Software
7. Networking with the Simulated Target System
8. Intel® Simics® Scripting
9. Software Debug Examples with Intel® Simics® Simulator
10. Document Revision History for Intel® Simics® Simulator for Intel FPGAs User Guide
A. Intel® Simics® Simulator Command Reference

5.5.2. CPU Cycles and Steps

The CPU cycle time is defined by the CPU frequency. In a single-processor system, the length (in seconds) of a clock cycle is easily defined as:

cycle=1/fcpu

where fcpu corresponds to the current CPU frequency.

The simulation of the execution of one single instruction is called a step. The step-rate corresponds to the number of steps executed each cycle (not including stalling). Similarly, the cycles per Instruction (CPI) corresponds to the number of clock cycles that are required to execute one instruction. Normally, the CPI corresponds to the reciprocal of the step-rate. The following figure describes these concepts:

Figure 8. Representation of Steps and Cycles Concepts in Intel® Simics® Simulator Timing Context

You can obtain the CPI parameter for a processor using the [processor_path].info command. You can use the [processor_path].set-step-rate command to get the step rate read as steps/cycle (can be used also to update this parameter which can be used to tweak the simulation performance, but Intel does not recommend modifying this parameter as this has not been properly verified). The following capture shows an example to retrieve the step-rate and the CPI of a processor: 

# Intel Simics simulator CLI

simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].info

Information about system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0] [class arm-cortex-a55]
==============================================================================

         VMP status : Not Loaded
    JIT compilation : Enabled
    Clock frequency : 400 MHz
                CPI : 1.00
    Physical memory : system.board.fpga.soc_inst.hps_subsys.agilex_hps.cpu_mem[0]
               Cell : system.cell
simics> system.board.fpga.soc_inst.hps_subsys.agilex_hps.core[0].set-step-rate 
Current step rate is 1/1

In the above example, you can observe that for the core[0], the initial CPI value is 1.00, and the current step-rate is 1 step per 1 cycle.

Intel® Simics® allows you to inspect what the current simulation time is for a specific core using the ptime (print-time) command. This command also allows you to get the number of cycles and number of steps (instructions) that the CPU has executed. The syntax of this command is as follow: 

ptime [cpu-name] [-s] [-c] [-t] [-pico-seconds] [-all]

Where:

  • -s: Indicates the number of steps executed.
  • -c: Indicates the number of cycles executed.
  • -t: Indicates the execution time.
  • -pico-seconds: Indicates the execution time in pico seconds.

This command acts over the CPU that is provided in the cpu-name argument or over the current CPU selected (indicated with psel command if this argument is not provided). If the -all argument is provided it prints the information for all the CPUs.

The following capture shows some examples that describe how the ptime command operates. For this, the run command is used to advance a specific number of cycles or steps in the simulation. 

# Intel Simics simulator CLI  
# In this example, the step rate is 1/1., CPI is 1 and CPU0 frequency is 80 MHz 
simics> ptime 
----------------------------------------------------------
Processor                    Steps     Cycles     Time (s)
----------------------------------------------------------
system...agilex_hps.core[0]  82723967  82724049   1.000
----------------------------------------------------------

simics> ptime -pico-seconds 
-------------------------------------------
    Processor                 Picoseconds 
-------------------------------------------
system...agilex_hps.core[0]   999999990000
-------------------------------------------

simics> run 1000 cycles 
simics> ptime 
-----------------------------------------------------------
Processor                    Steps     Cycles      Time (s)
-----------------------------------------------------------
system...agilex_hps.core[0]  82724967  82725049    1.000
-----------------------------------------------------------

simics> ptime -pico-seconds 
--------------------------------------------
Processor                      Picoseconds 
--------------------------------------------
system...agilex_hps.core[0]    1000012490000
--------------------------------------------

simics> run 2000 steps 
simics> ptime 
-----------------------------------------------------------
Processor                    Steps     Cycles      Time (s)
-----------------------------------------------------------
system...agilex_hps.core[0]  82726967  82727049    1.000
-----------------------------------------------------------

simics> ptime -pico-seconds 
--------------------------------------------
Processor                      Picoseconds 
--------------------------------------------
system...agilex_hps.core[0]    1000037490000
--------------------------------------------

In the previous example, the cycle time is 12500 ps based on the 80 MHz CPU frequency. Initially, you are calling ptime command to determine the current time, number of cycles, and steps for the selected processor (Core 0). Here, the simulation time is obtained also in pico seconds. Next, the simulation is run for 1000 cycles. You then read the new current time/steps/cycles and observe that the number of cycles is increased exactly in 1000 cycle, which matches our expectation. Also, as the CPI is 1, then it means that the number of steps must be increased by 1000. Also, you can verify that the simulation time was increased by 12,500,000 that matches the expected value (number cycles * cycle time). The exercise is repeated but this time the simulation is run for 2000 steps. In this case, because the CPI is 1, it means that it also must advance 2000 cycles and 25,000,000 ps.

Besides the run commands that were presented earlier, there are specific commands that allow you to run a certain number of steps or cycles providing as an additional information the assembler instructions that were executed. These commands are the following: 

step-instruction [count] [-r] [-q]
step-cycle [count]

The step-instruction command advances count number of instructions in the simulation. If -r argument is provided, the register changes are also printed. If -q argument is provided, the assembler instruction is not printed.

The step-cycle command advances count number of cycles in the simulation. This command also prints instructions that are being executed: 

# Intel Simics simulator CLI 

# Running 5 steps using stepi command
simics> stepi 5
[system...agilex_hps.core[0]] v:0xffff800008010a84 p:0x8000000002010a84  add sp, sp, x0
[system...agilex_hps.core[0]] v:0xffff800008010a88 p:0x8000000002010a88  sub x0, sp, x0
[system...agilex_hps.core[0]] v:0xffff800008010a8c p:0x8000000002010a8c  tbnz w0, #14, 0xffff800008010a9c
[system...agilex_hps.core[0]] v:0xffff800008010a90 p:0x8000000002010a90  sub x0, sp, x0
[system...agilex_hps.core[0]] v:0xffff800008010a94 p:0x8000000002010a94  sub sp, sp, x0

# Run 3 cycles using step-cycle command
simics> step-cycle 3
[system...agilex_hps.core[0]] v:0xffff800008011334 p:0x8000000002011334  stp x28, x29, [sp, #224]
[system...agilex_hps.core[0]] v:0xffff800008011338 p:0x8000000002011338  add x21, sp, #0x150
[system...agilex_hps.core[0]] v:0xffff80000801133c p:0x800000000201133c  mrs x28, sp_el0
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