F-Tile Low Latency 50G Ethernet Intel® FPGA IP Release Notes

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ID 778602
Date 7/08/2024
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Document Table of Contents x
1. F-Tile Low Latency 50G Intel FPGA IP Release Notes
1. F-Tile Low Latency 50G Intel FPGA IP Release Notes x
1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v6.0.0 1.2. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v5.0.0 1.3. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v4.0.0 1.4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v3.0.0 1.5. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v2.0.0 1.6. F-Tile Low Latency 50G Ethernet Intel FPGA IP v1.0.1 1.7. F-Tile Low Latency 50G Ethernet Intel FPGA IP v1.0.0
1. F-Tile Low Latency 50G Intel FPGA IP Release Notes

1.2. F-Tile Low Latency 50G Ethernet Intel® FPGA IP v5.0.0

Table 2.  v5.0.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Utilized o_clk_rec_div64 (recovered clock) in the Rx PMA interface, instead of o_clk_pll (system pll clock) for the Rx MAC interface (i_clk_rx). Here, the system clock PLL output is used instead of the recovered clock. —
Level Two Title