Ethernet Subsystem Intel® FPGA IP Release Notes

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ID 776967
Date 11/04/2024
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1. Ethernet Subsystem Intel® FPGA IP Release Notes
1. Ethernet Subsystem Intel® FPGA IP Release Notes x
1.1. Ethernet Subsystem Intel® FPGA IP v27.0.0 1.2. Ethernet Subsystem Intel® FPGA IP v26.0.0 1.3. Ethernet Subsystem Intel® FPGA IP v25.0.0 1.4. Ethernet Subsystem Intel® FPGA IP v24.0.0 1.5. Ethernet Subsystem Intel® FPGA IP v23.0.0 1.6. Ethernet Subsystem Intel® FPGA IP v22.6.0 1.7. Ethernet Subsystem Intel® FPGA IP v22.5.0 1.8. Ethernet Subsystem Intel® FPGA IP User Guide Archives
1. Ethernet Subsystem Intel® FPGA IP Release Notes

1.2. Ethernet Subsystem Intel® FPGA IP v26.0.0

Table 2.  v26.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2 Added new parameter: Enable Multi Tile. —
Added Analog Parameters tab in the IP GUI. Analog settings can now be configured through either the IP GUI or the .qsf file.
Added the following parameters for F-Tile variant:
  • SYSPLL_RATE_GUI
  • SYSPLL_CUSTOM_GUI
Selects the system PLL rate when custom mode is enabled.
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