Ethernet Subsystem Intel® FPGA IP Release Notes

Download PDF
ID 776967
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Ethernet Subsystem Intel® FPGA IP Release Notes
1. Ethernet Subsystem Intel® FPGA IP Release Notes x
1.1. Ethernet Subsystem Intel® FPGA IP v27.0.0 1.2. Ethernet Subsystem Intel® FPGA IP v26.0.0 1.3. Ethernet Subsystem Intel® FPGA IP v25.0.0 1.4. Ethernet Subsystem Intel® FPGA IP v24.0.0 1.5. Ethernet Subsystem Intel® FPGA IP v23.0.0 1.6. Ethernet Subsystem Intel® FPGA IP v22.6.0 1.7. Ethernet Subsystem Intel® FPGA IP v22.5.0 1.8. Ethernet Subsystem Intel® FPGA IP User Guide Archives
1. Ethernet Subsystem Intel® FPGA IP Release Notes

1.3. Ethernet Subsystem Intel® FPGA IP v25.0.0

Table 3.  v25.0.0 2024.04.15
Quartus® Prime Version Description Impact
24.1 Changed Nios® implementation from Nios® II to Nios® V. IP's device utilization numbers have changed.
Added the following port profiles for F-Tile:
  • 100GCAUI-4
  • 100GAUI-4
The current release supports these profiles for F-Tile.

Some Intel® FPGA IP products that previously included a Nios® II processor now use a Nios® V processor.

If you do not have a valid Nios® V license, you might receive an error message when you generate programming files for a design that includes these Intel® FPGA IP products.

For details and a workaround, refer to Why do I get an error in generating programming files and it shows as invalid license for Nios® V Processor for Intel® FPGA in the Quartus® Prime Pro Edition software version 24.1? in the Intel® FPGA Knowledge Base.

Level Two Title