High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide

An automated design example flow is available for the High Bandwidth Memory (HBM2E) Interface FPGA IP. The HBM2E IP can generate design example file sets for synthesis and simulation.

You can use the Example Design tab and the Generate Example Design button in the HBM2E FPGA IP IP Parameter Editor window to specify and generate synthesis and simulation example design file sets with which you can validate your HBM2E IP.

The generated design example reflects the parameterization that you set in the IP Parameter Editor window.

Intel provides a simulation and compilation-only design example that you can use to see the functionality of the IP and estimate the IP core area.

Note: The design example includes all needed NoC components; however, the abstract NoC model used in simulation does not reflect the true HBM2E throughput of Agilex™ 7 M-Series devices.
Figure 1. General Design Example Flow


Section Content
Creating an Quartus Prime Project for Your HBM2E System
Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP
Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation
Compiling and Programming the Agilex 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example
Using the HBM2E Design Example with the Test Engine IP
Enabling and Using the HBM2E Design Example with the Performance Monitor
Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation
Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP

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