External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

11.1. Interface Configuration Performance Issues

There are many interface combinations and configurations possible in an Altera design, therefore it is impractical for Altera to explicitly state the achievable fMAX for every combination.

Altera seeks to provide guidance on typical performance, but this data is subject to memory component timing characteristics, interface widths, depths directly affecting timing deration requirements, and the achieved skew and timing numbers for a specific PCB.

FPGA timing issues should generally not be affected by interface loading or layout characteristics. In general, the Altera performance figures for any given device family and speed-grade combination should usually be achievable.

To resolve FPGA (PHY and PHY reset) timing issues, refer to the Timing Closure chapter.

Achievable interface timing (address and command, half-rate address and command, read and write capture) is directly affected by any layout issues (skew), loading issues (deration), signal integrity issues (crosstalk timing deration), and component speed grades (memory timing size and tolerance). Altera performance figures are typically stated for the default (single rank, unbuffered DIMM) case. Altera provides additional expected performance data where possible, but the fMAX is not achievable in all configurations. Altera recommends that you optimize the following items whenever interface timing issues occur:

  • Improve PCB layout tolerances
  • Use a faster speed grade of memory component
  • Ensure that the interface is fully and correctly terminated
  • Reduce the loading (reduce the deration factor)