External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 7/08/2024
Public
Document Table of Contents

7.2.3.1. General Guidelines - DDR5

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Agilex™ 7 M-Series devices, whether you are using the hard memory controller or your own solution.
Note: QDRx is not supported with HPS.

Observe the following general guidelines when placing pins for your Agilex™ 7 M-Series external memory interface:

  1. Ensure that the pins of a single external memory interface reside on the same edge I/O.
  2. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the table in the Address and Command Pin Placement for DDR5 topic.
  3. Not every byte lane can function as an address and command lane or a data lane. The pin assignment must adhere to the DDR5 data width mapping defined in DDR5 Data Width Mapping .
  4. A byte lane must not be used by both address and command pins and data pins.
  5. An external memory interface can occupy one or more banks on the same edge. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
    • If an I/O bank is shared between two interfaces—meaning that two sub-banks belong to two different EMIF interfaces—then both the interfaces must share the same voltage.
    • Sharing of I/O lanes within a sub-bank for two different EMIF interfaces is not permitted; I/O lanes within a sub-bank can be assigned to one EMIF interface only.
  6. Any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin:
    • For fabric EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same sub-bank, pins in an I/O lane that is not assigned to an EMIF interface, can be used as general-purpose I/O pins.
    • For HPS EMIF, unused pins in an I/O lane assigned to an EMIF interface cannot be used as general-purpose I/O pins. In the same bank, pins in an I/O lane that is not assigned to an EMIF interface cannot be used as general-purpose I/O pins either.
  7. All address and command pins and their associated clock pins (CK_t and CK_c) must reside within a single sub-bank. The sub-bank containing the address and command pins is identified as the address and command sub-bank. Refer to the table in DDR5 Data Width Mapping for the supported address and command and data lane placements for DDR5.
  8. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Agilex™ 7 M-Series External Memory Interface Pin Information file.
  9. An external memory interface can occupy one or more banks on the same edge. When an interface must occupy multiple banks, ensure the following:
    • That the banks are adjacent to one another.
    • That you used only the supported data width mapping as defined in the table in DDR5 Data Width Mapping . Be aware that not every byte lane can be used as an address and command lane or a data lane.
    The following figure shows one possible pin placement for a DDR5 2ch x32 + ECC interface on Bank 2C and Bank 2D.
    Figure 31. x72 DDR5 Pin Placement using Bank 2C and 2D
  10. An unused I/O lane in the address and command sub-bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
  11. An I/O lane must not be used by both address and command pins and data pins.
  12. Place read data groups according to the DQS grouping in the pin table and Pin Planner. Read data strobes (such as DQS_t and DQS_c) must reside at physical pins capable of functioning as DQS_t and DQS_c for a specific read data group size. You must place the associated read data pins (DQ), within the same group.
    Note: For DDR5 interfaces with x4 components, place DQ pins and DQS entirely in either the upper or lower half of a 12-bit bank sub-group. Consult the pin table for your device to identify the association between DQ pins and DQS pins for x4 mode operation. Additional restrictions apply for x4/x8 DIMM interoperability.
  13. One of the sub-banks in the device (typically the sub-bank within corner bank 3A) may not be available if you use certain device configuration schemes. For some schemes, there may be an I/O lane available for EMIF data group.
    • AVST-8 – This is contained entirely within the SDM, therefore all lanes of sub-bank 3A can be used by the external memory interface.
    • AVST-16/AVST-32– Lanes 4, 5, 6, and 7 are all effectively occupied and are not usable by the external memory interface.
  14. Two memory interfaces cannot share an I/O 48 sub-bank.