Visible to Intel only — GUID: yhs1718380145641
Ixiasoft
Visible to Intel only — GUID: yhs1718380145641
Ixiasoft
10.4.3. AXI to Memory Mapping
The default configuration is as follows:
<MSB | LSB> | |||||||
---|---|---|---|---|---|---|---|---|
Chip Select | Chip ID | Row | Bank | Bank Group [1] | Column [N:3] | Bank Group [0] | Column [2:0] | Datapath |
<MSB | LSB> | |||||||
---|---|---|---|---|---|---|---|---|
Chip Select | Chip ID | Row | Bank | Bank Group [2] | Column [N:3] | Bank Group [1:0] | Column [2:0] | Datapath |
Datapath: For a x32 or wider interface, two bits are allocated to datapath. For a x16 interface, one bit is allocated; this bit should always be set to zero.
Row/Bank/Bank Group/Column: These are allocated a number of address bits based on the requirements of the connected memory type.
Chip Select/Chip ID: These are each one bit wide and are omitted when not using multi-rank or 3DS configurations.
Example: AXI Address mapping for a DDR4 1Gb x8 device, 2 components per rank for a total DQ Width of x16
You can obtain addressing tables from your memory device datasheet. For this example, the following information applies:
Parameter | 1 Gb x 8 |
Bank Group | BG[1:0] |
Bank Address | BA[1:0] |
Rows | A[15:0] |
Columns | A[9:0] |
The following AXI Address to Memory Mapping table can be constructed.
Memory Address Bits | AXI Address Bits |
---|---|
Datapath [0] | [0] - Always 0, 1 bit for x16 interfaces |
Column [2:0] | [3:1] |
BG [0] | [4] |
Column [9:3] | [11:5] |
BG [1] | [12] |
BA [1:0] | [14:13] |
Row [15:0] | [30:15] |
Using this information, the AXI Address to write to Column 1016 of the Row 0, Bank group 0, Bank 0 is: 0x00000FE0.