External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
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7.4.8. DDR5 PCB Layout Guidelines
Agilex™ 7 M-Series devices support DDR5 interfaces for both discrete components and DIMMs, RDIMMs, SODIMMs, and LRDIMMs, with both thin and thick PCB stackups. The maximum supported data rates vary depending on the selected topology and thickness of circuit board.
Section Content
DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16
Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations
Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations
Example of a DDR5 layout on an Altera FPGA Platform Board