5. Known Issues and Workarounds
FPGA AI Suite Version 2024.1 has the following known issues:
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The Layout Transform module in the IP is a preproduction feature. This module offloads all image preprocessing from the host CPU to the FPGA device. It is similar to the layout transform included in the S2M variant of the SoC design example, but is more flexible and enables higher performance for many graphs. The Layout Transform module has the following known issues:
- Executing inferences with the OpenVINO™ ASYNC API and with more than one inference requests causes the OpenVINO™ runtime to timeout while waiting for incomplete inferences. For instance, running the dla_benchmark command with Resnet50 and the command options -api async -niter 2 on a design compiled with the layout transform enabled completes only one of the two scheduled inferences.
- Executing inferences with batch sizes greater than one cause the runtime to hang after one inference. FPGA AI Suite Version 2024.1 only supports batch = 1 .
- Due to an internal issue in the layout transform, model accuracy may be slightly diminished for some models when the layout transform is enabled.
- In FPGA AI Suite: Version 2024.1, to enable the layout transform, exact parameters for the target model input convolution must be specified in the overlay architecture. The implication is that each bitstream is compatible only with one model or family of models.
The full featured layout transform module allows for runtime configurability of these parameters and only maximum values will be specified in the overlay architecture.
- In FPGA AI Suite: Version 2024.1, the IP stream buffer specified in the .arch file must be large enough to ensure that the graph is not "sliced" at the input layer by the FPGA AI Suite compiler (dla_compiler). The compiler prints an error message if this condition is not met when the layout transform is enabled.
- FPGA AI Suite Version 2024.1, testing and validation of the Layout Transform module is limited to the PCIe-attach design examples. Other design examples are planned to be tested and validated for a future release.