FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/31/2024
Public
Document Table of Contents

3.6.3. Compiling the Graphs

The precompiled SD card image (.wic) provided with the FPGA AI Suite uses one of the following files as the IP architecture configuration file:
  • Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit
    AGX7_Performance.arch
  • Arria® 10 SX SoC FPGA Development Kit
    A10_Performance.arch
To create the AOT file for the M2M variant (which uses the dla_benchmark utility), run the following command:
cd $COREDLA_WORK/demo/models/public/resnet-50-tf/FP32
dla_compiler \
--march $COREDLA_ROOT/example_architectures/<IP arch config file> \
--network-file ./resnet-50-tf.xml \
--foutput-format=open_vino_hetero \
--o $COREDLA_WORK/demo/RN50_Performance_b1.bin \
--batch-size=1 \
--fanalyze-performance

where <IP arch config file> is one of the IP architecture configuration files listed earlier.

To create the AOT file for the S2M variant (which uses the streaming inference app), run the following command:
cd $COREDLA_WORK/demo/models/public/resnet-50-tf/FP32
dla_compiler \
--march $COREDLA_ROOT/example_architectures/<IP arch config file> \
--network-file ./resnet-50-tf.xml \
--foutput-format=open_vino_hetero \
--o $COREDLA_WORK/demo/RN50_Performance_no_folding.bin \
--batch-size=1 \
--fanalyze-performance \
--ffolding-option=0

where <IP arch config file> is one of the IP architecture configuration files listed earlier.

After running either these commands, the compiled models and demonstration files are in the following locations:

Compiled Models

$COREDLA_WORK/demo/RN50_Performance_b1.bin

$COREDLA_WORK/demo/RN50_Performance_no_folding.bin

Sample Images

$COREDLA_WORK/demo/sample_images/

Architecture File

$COREDLA_ROOT/example_architectures/AGX7_Performance.arch

or

$COREDLA_ROOT/example_architectures/A10_Performance.arch