Visible to Intel only — GUID: jwl1678993627185
Ixiasoft
Visible to Intel only — GUID: jwl1678993627185
Ixiasoft
8.2. Building the Stream Controller Module
The stream controller is built as part of the steps described in Installing HPS Disk Image Build Prerequisites. For system development that extends the FPGA AI Suite SoC design example, you might want to compile the stream controller module independently.
The stream controller module source code can be found in the distribution, in the runtime/coredla_device/stream_controller/ directory.
There is a script build.sh in the source code directory that builds a binary .hex file. This file is then used by Quartus® Prime when building the firmware to embed the microcode module.
The script should be run from a Nios® V command shell, which is part of Quartus® Prime. It requires a Quartus® Prime project file and a Quartus® Prime .qsys file. For this design example, the project file is top.qpf, and the Platform Designer file is dla.qsys.
./build.sh top.qpf dla.qsys stream_controller.hex