Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6. Fabric EMIF Design Component

The design provides a 266MHz DDR4-64Bit Avalon® -based memory controller. This EMIF is used solely by the DLA.

The Intel® FPGA AI Suite IP memory interface is configured to be 512 bits wide. The EMIF interface is setup to complement this configuration.