FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

6.1. Build Script

While this design example includes prepackaged bitstreams, you can also use the build script to build bitstreams.

To build the PCIe-based example design, use the bin/dla_build_example_design.py script. You can use this script to create an example design with one or multiple FPGA AI Suite IP instances.

The script generates a wrapper that wraps one or more IP instances along with adapters necessary to connect to the Terasic DE10-Agilex BSP or to the OPAE BSP ( Arria® 10).

When specifying an <architecture_file>, pay attention to the resource limitations on the FPGA, as well as the number of resources that the board support package (BSP) uses.

The dla_compiler tool includes a --fanalyze-area option to estimate the resources required for a single IP instance corresponding to an architecture file, as described in the FPGA AI Suite Compiler Reference Manual.

Implementing two instances (as is the default for dla_build_example_design.py) requires twice the resources.

Table 4.  Build Script Resources
Resources ALMs M20k DSPs
Resources available on Arria® 10 1150 device 427200 2713 1518
Reasonable Target Utilization 80% 90% 90%
Usable Resources 342000 2445 1365
Resources needed for BSP 62000 330 0
Resources available for IP instances 280000 2115 1365

The OPAE BSP used by the Intel PAC with Arria® 10 GC FPGA board is compatible only with bitstreams for accelerator function units (AFUs) compiled with Quartus® Prime Pro Edition Version 19.2. An AFU and its associated accelerator functions (AFs) are sometimes referred to as the green bitstream or green bits. For more details OPAE bitstream types, refer to Design Example Microarchitecture.

The DE10-Agilex design is only validated for use with Quartus® Prime Pro Edition Version 23.4. This Agilex™ 7 design does not use the Quartus® Prime partial reconfiguration feature, unlike the OPAE BSP. The Agilex device has significantly more resources and can support up to four IP instances.


Section Content
Build Script Options
Script Flow

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