FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

5.4. Programming the FPGA Device ( Arria® 10)

You can verify the Intel® PAC with Arria® 10 GX FPGA programming by OPAE by using one of the OPAE sample application programs.

The OPAE sample application programs are described in the Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Arria® 10 GX FPGA.

If the Intel PAC is connected and has sufficient cooling, then you can program a bitstream using the fpgaconf command. If the demonstration bitstreams (which correspond to the architectures in the example_architectures/ directory) were installed, then you can use them. You can also compile a new bitstream, as described in section Compiling the PCIe -based Example Design.

You can program the design example bitstreams by using the following command: 

fpgaconf -v  <path_to_design_example_bitstream (.gbs)>

The Intel® PAC with Arria® 10 GX FPGA requires server-level cooling with a dual-fan graphics card cooler or another appropriate fan. Contact your Intel representative for specific cooling solution suggestions and quote case 14016255788 when contacting your representative.

If the supplementary cooling is not sufficient, the PAC will hang during inference. Until you are certain that the cooling solution is sufficient, monitor the temperature using the command: sudo fpgainfo temp

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