FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

6.1.2. Script Flow

The following steps describe the internal flow of the dla_build_example_design.py script for the Arria 10 PAC:
  1. Runs the dla_create_ip script to create an FPGA AI Suite IP for the requested FPGA AI Suite architecture
  2. Creates a wrapper around the FPGA AI Suite IP instances and adapter logic
  3. Runs the OPAE afu_synth_setup script to create a build directory that has the BSP infrastructure needed to compile the design with Quartus® Prime software.
  4. Runs the OPAE run.sh script to compile the design example with Quartus® Prime software:
    1. Compile the example design up to and including bitstream generation.
    2. Analyze the timing report to extract the FPGA AI Suite clock maximum frequency (fMAX).
    3. Create an AFU/AF bitstream (green bitstream) file with PLL configurations to generate a clock that is slightly lower than the fMAX of the design.
  5. Runs the OPAE PACSign script to generate an unsigned version of the AFU/AF bitstream as well as a signed version.

The script uses the Quartus® Prime timing analyzer to report the top critical paths of the compiled design example.

The unsigned and signed versions of the bitstreams are in the <build_dir> directory that you set when running the script (or the default location, if you did not set it). The signed and unsigned bitstream file names are dla_afu.gbs and dla_afu_unsigned.gbs, respectively.

The Quartus® Prime compilation reports are available in the <build_dir>/build/output_files directory. A build.log file that has all the output log for running the build script is available in the <build_dir> directory. In addition, the achieved FPGA AI Suite clock frequency is the clock-frequency-low value in the following file:

<build_dir>/build/output_files/user_clock_freq.txt

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