Intel® FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 9/06/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example 4. Building the Intel® FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the Intel® FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the Intel FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Intel® Arria® 10) 5.5. Programming the FPGA Device ( Intel Agilex® 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. Intel FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example
4. Building the Intel® FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives
B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

1. Intel® FPGA AI Suite PCIe-based Design Example User Guide

Updated for:
Intel® FPGA AI Suite 2023.2.1

The Intel® FPGA AI Suite PCIe* -based Design Example User Guide describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® PAC with Intel® Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board

The following sections in this document describe the steps to build and execute the design:
The following sections in this document describe design decisions and architectural details about the design:

Use this document to help you understand how to create a PCIe example design with the targeted Intel® FPGA AI Suite architecture and number of instances and compiling the design for use with the Intel FPGA Basic Building Blocks (BBBs) system.

About the Intel® FPGA AI Suite Documentation Library

Documentation for the Intel® FPGA AI Suite is split across a few publications. Use the following table to find the publication that contains the Intel® FPGA AI Suite information that you are looking for:
Table 1.   Intel® FPGA AI Suite Documentation Library
Title and Description  
Release Notes

Provides late-breaking information about the Intel® FPGA AI Suite including new features, important bug fixes, and known issues.

Link
Getting Started Guide

Get up and running with the Intel® FPGA AI Suite by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® FPGA AI Suite

Link
IP Reference Manual

Provides an overview of the Intel® FPGA AI Suite IP and the parameters you can set to customize it. This document also covers the Intel® FPGA AI Suite IP generation utility.

Link
Compiler Reference Manual

Describes the use modes of the graph compiler (dla_compiler). It also provides details about the compiler command options and the format of compilation inputs and outputs.

Link
PCIe-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® PAC with Intel® Arria® 10 GX FPGA or a Terasic* DE10-Agilex Development Board.

Link
SoC-based Design Example User Guide

Describes the design and implementation for accelerating AI inference using the Intel® FPGA AI Suite, Intel® Distribution of OpenVINO™ Toolkit, and an Intel® Arria® 10 SX SoC FPGA Development Kit.

Link

Intel® Distribution of OpenVINO™ Toolkit Requirement

To use the Intel® FPGA AI Suite, you must be familiar with the Intel® Distribution of OpenVINO™ Toolkit.

Intel® FPGA AI Suite Version 2023.2.1 requires the Intel® Distribution of OpenVINO™ Toolkit Version 2022.3.1 LTS. For OpenVINO™ documentation, refer to https://docs.openvino.ai/2022.3/documentation.html.

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