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1. Intel® FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example
4. Building the Intel® FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives
B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the Intel FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Intel® Arria® 10)
5.5. Programming the FPGA Device ( Intel Agilex® 7)
5.6. Performing Accelerated Inference with the dla_benchmark Application
5.7. Running the Ported OpenVINO™ Demonstration Applications
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7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
The Intel PAC with Intel® Arria® 10 GX FPGA design example is derived from the OpenCL BSP provided with the Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs (which also includes OPAE technology).
The Intel Acceleration Stack is designed to make FPGAs usable as accelerators. On the FPGA side, the Intel Acceleration Stack splits acceleration functions into two parts:
- The FPGA interface manager (FIM) is FPGA hardware that contains the FPGA interface unit (FIU) and external interfaces for functions like memory access and networking. The FIM is locked and cannot be changed. The FIM is sometimes referred to as BBS, blue bits, or blue bitstream.
- The accelerator function (AF) is a compiled accelerator image implemented in FPGA logic that accelerates an application. AFs are compiled from accelerator functional units (AFUs). An AFU and associated AFs are sometimes referred to as GBS, green bits, or green bitstream. An FPGA device can be reprogrammed while leaving the FIM in place.
The FIM handles external interfaces to the host, to which it is connected via PCIe. On the host side, a driver stack communicates with the AFU via the FIM. This is referred to as OPAE (Open Programmable Acceleration Engine). OPAE talks to the AFU with the CCI-P (core cache interface) protocol that provides an abstraction over PCIe protocol.