FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2024
Public
Document Table of Contents

2.3. Software Emulation of the FPGA AI Suite IP

The FPGA AI Suite includes a C++ software model of the FPGA AI Suite IP that is bit-accurate*. The emulation of the FPGA AI Suite IP is accessible through the OpenVINO™ plugin interface. This emulation models the numeric details of the IP, including the behavior of the block floating point numerics (when used).

The emulation OpenVINO™ plugins are enabled in the $COREDLA_ROOT/bin/plugins_reference.xml plugins file. Because it uses the OpenVINO™ plugin architecture, it works with both the OpenVINO™ Python API and the C++ API. For an example that shows how to use emulation as the inference engine for the runtime dla_benchmark utility, refer to " Performing Inference Without an FPGA Board " in the FPGA AI Suite Getting Started Guide .

Because the emulation executes on the CPU and does not benefit from the FPGA acceleration, the emulation is much slower than inference on the FPGA. Typical inference times for a single image with ResNet50 are on the order of minutes of time. The inference speed varies dramatically depending on the architecture configuration and the graph.

* Minor rounding differences between software emulation and hardware will typically result in differences of less than two units of least precision (ULPs).