FPGA AI Suite: IP Reference Manual

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ID 768974
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite IP Reference Manual 2. About the FPGA AI Suite IP 3. FPGA AI Suite IP Generation Utility 4. FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. FPGA AI Suite IP Reference Manual Archives B. FPGA AI Suite IP Reference Manual Document Revision History
2. About the FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Software Emulation of the FPGA AI Suite IP 2.4. FPGA AI Suite Layer / Primitive Ranges 2.5. FPGA AI Suite IP Block Configuration 2.6. IP Block Interfaces 2.7. Feature Input and Output Streaming 2.8. DDR-Free Operation
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.5. FPGA AI Suite IP Block Configuration x
2.5.1. Architecture Description File Format for Instance Parameterization 2.5.2. Architecture Description File Parameters
2.5.2. Architecture Description File Parameters x
2.5.2.1. Parameter Group: Global Parameters 2.5.2.2. Parameter Group: activation 2.5.2.3. Parameter Group: pe_array 2.5.2.4. Parameter Group: pool 2.5.2.5. Parameter Group: depthwise 2.5.2.6. Module: softmax 2.5.2.7. Parameter Group: dma 2.5.2.8. Parameter Group: xbar 2.5.2.9. Parameter Group: filter_scratchpad 2.5.2.10. Parameter Group: input_stream_interface 2.5.2.11. Parameter Group: output_stream_interface 2.5.2.12. Parameter Group: config_network 2.5.2.13. (Early Access) Parameter Group: layout_transform_params
2.6. IP Block Interfaces x
2.6.1. Clock and Reset 2.6.2. AXI Interfaces 2.6.3. AXI Interface Clock and Reset 2.6.4. Input Feature Tensor In-Memory Format 2.6.5. Output Tensor In-Memory Format
2.6.4. Input Feature Tensor In-Memory Format x
2.6.4.1. Multiple Input Graphs 2.6.4.2. Input Folding 2.6.4.3. Input Scale and Shift 2.6.4.4. Input Transform Mapping 2.6.4.5. Input Layout Transform Hardware
2.7. Feature Input and Output Streaming x
2.7.1. Input Streaming 2.7.2. Output Streaming
3. FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers 5.7. DMA License Register
1. FPGA AI Suite IP Reference Manual
2. About the FPGA AI Suite IP
3. FPGA AI Suite IP Generation Utility
4. FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. FPGA AI Suite IP Reference Manual Archives
B. FPGA AI Suite IP Reference Manual Document Revision History

B. FPGA AI Suite IP Reference Manual Document Revision History

Document Version FPGA AI SuiteVersion Changes
2024.09.06 2024.2
  • Replaced occurrences of "memoryless" with "DDR-free".
  • Renamed "FPGA AI Suite Software Reference Model" to "Software Emulation of the FPGA AI Suite IP ".
  • Replaced occurrences of "software reference model" with "software emulation model".
2024.07.31 2024.2
  • Added "FPGA AI Suite Software Reference Model"
  • Updated "FPGA AI Suite Layer/Primitive Ranges" as follows:
    • Added Tanh
    • Revised Max Pool window size range
    • Revised pool max_windows_height/width valid range
  • Updated "FPGA AI Suite IP Block Configuration" as follows:
    • Added enable_parameter_rom
    • Added enable_tanh
  • Updated "Parameter Group: Global Parameters" as follows:
    • Revised description of arch_precision parameter
    • Added section Parameters: output_image_height_max, output_image_width_max, output_channels_max
  • Updated "Parameter Group: activation " to add Parameter: activation/enable_tanh
  • Added "Parameter Group: input_stream_interface "
  • Added "Parameter Group: ouput_stream_interface "
  • Added "Feature Input and Output Streaming"
  • Added "Input Streaming"
  • Added "Output Streaming"
  • Added "Memoryless Operation"
  • Updated"DMA Control Registers" as follows:
    • Added IP_reset register
    • Added Activate_streaming register
2024.03.29 2024.1
  • Rebranded from "Intel FPGA AI Suite" to "FPGA AI Suite".
  • Added updates to support new dedicated layout transform module.
  • Updated "FPGA AI Suite Layer / Primitive Ranges" as follows:
    • Updated description of Softmax.
    • Added Sigmoid.
    • Added Swish.
  • Updated "FPGA AI Suite IP Block Configuration" as follows:
    • Expanded the ranges of the c_vector, pool k_vector, and activation k_vector parameters.
    • Added the enable_sigmoid parameter.
    • Expanded the range of the arch_precision parameter.
  • Updated "Parameter Group: Global Parameters" with additional information about Agilex™ 5 device family support.
  • Added activation/enable_sigmoid to "Parameter Group: activation ".
  • Added softmax/max_num_channels parameter description to "Module: softmax ".
2023.12.01 2023.3
  • Updated "Model Performance" with Version 2023.3 values
  • Updated arch_precision parameter description in "Parameter group: Global Parameters".
  • Added "Performance Registers".
  • Added "Debug Network Registers".
  • Added "PE scale precision" to " FPGA AI Suite IP Block Configuration".
  • Updated "Parameter Group: Global Parameters" for Agilex™ 5 support.
  • Updated "Parameter Group: pe_array " for Agilex™ 5 support.
2023.09.08 2023.2.1
  • Added Multilayer Perceptrons (MLPs) to supported models.
2023.07.03 2023.2
  • Updated "Model Performance" with Version 2023.2 values and the enabling of non-default Quartus® Prime options (register merging).
  • Added additional information about modifying the internal precision of a graph for performance improvement in "Architecture Description File Format for Instance Parameterization".
2023.04.05 2023.1
  • Added ChannelToSpace, DepthToSpace, and PixelShuffle to " FPGA AI Suite Layer / Primitive Ranges".
  • Added enable_debug to " FPGA AI Suite IP Block Configuration and Interfaces".
  • Added description of enable_round_clamp activation parameter where needed.
  • Added "Input Transform Mapping".
  • Added output transform mapping information to "Output Tensor In-Memory Format".
  • Renamed thedlac command. The FPGA AI Suite compiler command is now dla_compiler.
  • Updated "Model Performance" with Version 2023.1 values.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2023.02.03 2022.2
  • Correct the description of the -bgr option of the AOT splitter utility.
2022.12.23 2022.2
  • Added SqueezeNet to the list of supported models.
  • Added the family architecture description file global parameter.
  • Removed the --family IP generation utility command option.

2022.04.27

2022.1
  • Removed references to HLS generation.
  • Updated descriptions of parameters in the .arch file.
  • Added a Model Performance section.

2021.09.10

2021.2
  • Added information for Intel® Agilex™device support.
  • Added information for MobileNet v3 support.

2021.04.30

2021.1
  • Various corrections and updates.

2020.12.04

2020.2
  • Renamed Intel® FPGA AI Suite IP Core to Intel® FPGA AI Suite IP".

2020.10.30

2020.1
  • Initial release.
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