Intel® FPGA AI Suite: IP Reference Manual

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ID 768974
Date 9/06/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite IP Reference Manual 2. About the Intel® FPGA AI Suite IP 3. Intel® FPGA AI Suite IP Generation Utility 4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. Intel® FPGA AI Suite IP Reference Manual Archives B. Intel® FPGA AI Suite IP Reference Manual Document Revision History
2. About the Intel® FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Intel® FPGA AI Suite Layer / Primitive Ranges 2.4. Intel® FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. Intel® FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter group: Global Parameters 2.4.2.2. Parameter group: activation 2.4.2.3. Parameter group: pe_array 2.4.2.4. Parameter group: pool 2.4.2.5. Module: softmax 2.4.2.6. Parameter group: dma 2.4.2.7. Parameter group: xbar 2.4.2.8. Parameter group: filter_scratchpad 2.4.2.9. Parameter group: config_network
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping
3. Intel® FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers
1. Intel® FPGA AI Suite IP Reference Manual
2. About the Intel® FPGA AI Suite IP
3. Intel® FPGA AI Suite IP Generation Utility
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. Intel® FPGA AI Suite IP Reference Manual Archives
B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

Document Version Intel® FPGA AI SuiteVersion Changes
2023.09.08 2023.2.1
  • Added Multilayer Perceptrons (MLPs) to supported models.
2023.07.03 2023.2
  • Updated "Model Performance" with Version 2023.2 values and the enabling of non-default Intel® Quartus® Prime options (register merging).
  • Added additional information about modifying the internal precision of a graph for performance improvement in "Architecture Description File Format for Instance Parameterization".
2023.04.05 2023.1
  • Added ChannelToSpace, DepthToSpace, and PixelShuffle to " Intel® FPGA AI Suite Layer / Primitive Ranges".
  • Added enable_debug to " Intel® FPGA AI Suite IP Block Configuration and Interfaces".
  • Added description of enable_round_clamp activation parameter where needed.
  • Added "Input Transform Mapping".
  • Added output transform mapping information to "Output Tensor In-Memory Format".
  • Renamed thedlac command. The Intel® FPGA AI Suite compiler command is now dla_compiler.
  • Updated "Model Performance" with Version 2023.1 values.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2023.02.03 2022.2
  • Correct the description of the -bgr option of the AOT splitter utility.
2022.12.23 2022.2
  • Added SqueezeNet to the list of supported models.
  • Added the family architecture description file global parameter.
  • Removed the --family IP generation utility command option.

2022.04.27

2022.1
  • Removed references to HLS generation.
  • Updated descriptions of parameters in the .arch file.
  • Added a Model Performance section.

2021.09.10

2021.2
  • Added information for Intel® Agilex™device support.
  • Added information for MobileNet v3 support.

2021.04.30

2021.1
  • Various corrections and updates.

2020.12.04

2020.2
  • Renamed Intel® FPGA AI Suite IP Core to Intel® FPGA AI Suite IP".

2020.10.30

2020.1
  • Initial release.
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