Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2023
Public

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5. CSR Map and Descriptor Queue

The CSR interface uses a 32-bit data path in which all accesses are aligned to 32 bits; however the address is a byte address. The size of the CSR address space is 2048 bytes (11 bit addressable). The regions within the CSR address space are listed in the table that follows.

Table 7.  CSR Address Space Regions

Base Address

Feature

0x000

Discovery ROM (512 word)

0x200

Interrupt Control

0x210

DMA Descriptor Queue

0x220

DMA Control Registers

Register and Bit Attribute Definitions

The following notation describes the CSR registers.

Table 8.  Register and Bit Attribute Definitions

Attribute

Expansion

Description

RW

Read/Write

This bit can be read or written by software.

RO

Read Only

The bit is set by hardware only. Software can only read this bit. Writes have no effect.

RW1C

Read/Write 1to Clear

Software can read or clear this bit. Software must write 1 to clear this bit. Writing zero to an RW1C bit has no effect.

A multibit RW1C field can exist. In that case, all bits in the field are cleared if a 1 is written to any of the bits.

RsvdZ

Reserved and zero

Reserved for future RW1C implementations.

When you write to a register with RsvdZ bits, only write zeros to these bits.