Intel® FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 9/06/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Compiler Reference Manual 2. About the Intel® FPGA AI Suite Compiler 3. Intel® FPGA AI Suite Compiler Use Modes 4. Intel® FPGA AI Suite Compiler Command Line Options A. Intel® FPGA AI Suite Compiler Reference Manual Archives B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History
3. Intel® FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Estimating the Performance of a Graph 3.3. Estimating the Performance of a Partition of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. Intel® FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options) 4.9. Input File Formats for dla_compiler Command 4.10. Generation of Output File Formats 4.11. The Partitioning Table Report
1. Intel® FPGA AI Suite Compiler Reference Manual
2. About the Intel® FPGA AI Suite Compiler
3. Intel® FPGA AI Suite Compiler Use Modes
4. Intel® FPGA AI Suite Compiler Command Line Options
A. Intel® FPGA AI Suite Compiler Reference Manual Archives
B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History

4.4. Compilation Options (dla_compiler Command Options)

--foutput-format Option

Syntax
--foutput-format=<exported_graph_format>
Description
This option specifies the format of the exported compiled graph file.
The <exported_graph_format> parameter can take one of the following values:
  • open_vino_hetero
    The export function is called from the OpenVINO™ hetero plugin. This option serializes and dumps the following outputs to a binary file:
    • OpenVINO™ input information
    • OpenVINO™ output information
    • Intel® FPGA AI Suite compiled results
  • dla_compiled_result

    Only the Intel® FPGA AI Suite compiled results are dumped to the binary file.

Default Value
open_vino_hetero
Parsed As
(string)

--fplugin Option

Syntax

--fplugin=<OpenVINO_plugin>

Description
This option specifies the plugin for the OpenVINO™ inference engine.
The <OpenVINO_plugin> parameter can take one of the following values:
  • HETERO:FPGA

    The OpenVINO™ HETERO plugin is used, and it tries to use the FPGA for all inference operations.

    If any layers are not supported by the FPGA device, then it issues an error.

    Use this plugin to ensure that the CPU support is not used for any layers.

  • HETERO:CPU

    The OpenVINO™ HETERO plugin is used, and all inference operations are allocated to the CPU.

    Use this plugin to test the data flow through dla_benchmark application when an FPGA device is not available.

  • HETERO:FPGA,CPU

    The OpenVINO™ HETERO plugin is used, and inference operations are allocated to the FPGA device where possible. The CPU is used for layers that are not supported on the FPGA device.

    The graph is partitioned into parts that run on the FPGA device and parts that must run on the CPU.

Default Value
HETERO
Parsed As
(string)

--fassumed-fmax-core Option

Syntax
--fassumed-fmax-core=<assumed f MAX >
Description
This option sets the fMAX used for calculating performance. Specify the <assumed f MAX > value in MHz.
Default Value
256
Parsed As
(int)

--ffolding-option Option

Syntax
--ffolding-option=<folding_option>
Description
This option sets the folding mode that the compiler applies to the first convolution of the network to be executed on the FPGA device.
The <folding_option> parameter can take one of the following values:
  • 0

    No folding performed externally or by the Intel® FPGA AI Suite IP.

  • 1

    Folding performed externally (that is, by the host or a module outside of the Intel® FPGA AI Suite IP).

  • 2

    Folding performed externally, with additional folding performed by the Intel® FPGA AI Suite IP.

  • 3

    All folding performed by the Intel® FPGA AI Suite IP.

For more information about folding in the Intel® FPGA AI Suite, refer to the "Input Folding" section in the "Input Feature Tensor In-Memory" topic of Intel® FPGA AI Suite IP Reference Manual .

Default Value
3
Parsed As
(int)
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