Visible to Intel only — GUID: qjj1694010574265
Ixiasoft
Visible to Intel only — GUID: qjj1694010574265
Ixiasoft
1.2. Terminology for Intel Agilex® 7 M-Series FPGAs
Term | Description |
---|---|
NoC | Network-on-Chip based communications structure between elements only in Intel Agilex® 7 M-Series FPGAs. |
Hard Memory NoC | The NoC subsystem implemented as a hard block in the Agilex™ 7 M-Series FPGA for interfacing with high-bandwidth memory and external memory interfaces. |
Horizontal NoC (HNoC) | The Intel Agilex® 7 M-Series FPGA implements the NoC as two independent hard memory NoCs running horizontally along the top edge and bottom edge of the die. |
NoC Initiator (INIU) | The bridge between the AXI4 manager in user logic and the hard memory NoC. |
NoC Target (TNIU) | The bridge between the AXI4 subordinate IP in the periphery and the hard memory NoC. |
Fabric NoC | An optional implementation of the NoC initiator where the read response data is written directly to M20K memory blocks. |
HBM2E | The in-package, high-bandwidth memory available in Intel Agilex® 7 M-Series FPGAs. |
Pseudo BL8 Transaction | For HBM2E, you can enable data access granularity of 64B (64 bits per Pseudo-Channel at BL8) which can achieve greater efficiency. By default, data access granularity is 32B (64 bits per Pseudo-Channel at BL4). |
AXI4 Manager | Function that initiates transactions on an AXI4 interconnect. |
AXI4 Subordinate | Function that responds to transactions on an AXI4 interconnect. |
GPIO-B Blocks | General purpose I/O bank available in Intel Agilex® 7 M-Series FPGAs. |
Bypass Mode | Bypasses the NoC. This mode applies only to EMIF configuration, with EMIF in bypass mode. |
EMIF in bypass mode | Any instance of the External Memory Interfaces (EMIF) IP that you configure with PHY_NOC_EN=false. When PHY_NOC_EN=false, the access mode is through the fabric, in either sync or async mode). |
NoC PLL | Dedicated phase lock loop (PLL) for the hard memory NoC. |
Byte lane (BL) | Synonymous with an IO12, or I/O lane. |
NoC SSM | Subsystem manager for the hard memory NoC. |
Secure Device Manager (SDM) | There is no connection between the SDM and the hard memory NoC, and all signals from the SDM bypass the hard memory NoC. |
UIB | Universal interface block that is a silicon bridge to connect FPGA I/O to the HBM2E memory device. |
1d1r | one dimm, one rank |
1d2r | one dimm, two ranks |