Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

Download PDF
ID 768844
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs 3. NoC Design Flow in Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Agilex™ 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

3.6.3. Hard Memory NoC Locations in Interface Planner

When placing NoC initiators and targets, refer to Table 10. Top-Edge Hard Memory NoC Locations in Interface Planner and Table 11. Bottom-Edge Hard Memory NoC Locations in Interface Planner to correlate locations with Horizontal Bandwidth Considerations with NoC elements visible in the Interface Planner. In the following tables, the initiator and target locations in the same cell connect to the same switch in the hard memory NoC. Connections between initiators and targets using the same switch use a local connection instead of the high-speed horizontal links.

Table 10.  Top-Edge Hard Memory NoC Locations in Interface Planner
NoC Segment Initiator Interface Planner Location
PLL/SSM

NOCPLL_X11_Y417_N221

NOCSSM_X11_Y417_N220
GPIO-B_0 I0

NOCINITIATOR_X27_Y417_N202

NOCTARGET_X27_Y417_N200
I1

NOCINITIATOR_X42_Y417_N202

NOCAXILITETARGET_X42_Y417_N200
I2

NOCINITIATOR_X53_Y417_N202

NOCTARGET_X53_Y417_N200
GPIO-B_1 I0

NOCINITIATOR_X79_Y417_N202

NOCTARGET_X79_Y417_N200
I1

NOCINITIATOR_X94_Y417_N202

NOCAXILITETARGET_X94_Y417_N200
I2

NOCINITIATOR_X105_Y417_N202

NOCTARGET_X105_Y417_N200
UIB_L I0

NOCINITIATOR_X134_Y417_N202

NOCAXILITETARGET_X123_Y417_N200 (Visible in Chip Planner and Interface Planner but not user-accessible.)

NOCAXILITETARGET_X129_Y417_N200

NOCAXILITETARGET_X134_Y417_N200

NOCTARGET_X140_Y417_N200

NOCTARGET_X150_Y417_N200

I1

NOCINITIATOR_X150_Y417_N202

NOCTARGET_X156_Y417_N200

NOCTARGET_X161_Y417_N200

I2

NOCINITIATOR_X161_Y417_N202

NOCTARGET_X167_Y417_N200

UIB_M I0

NOCINITIATOR_X188_Y417_N202

NOCTARGET_X177_Y417_N200

NOCTARGET_X183_Y417_N200

I1

NOCINITIATOR_X204_Y417_N202

NOCTARGET_X188_Y417_N200

NOCTARGET_X210_Y417_N200

I2

NOCINITIATOR_X215_Y417_N202

NOCTARGET_X215_Y417_N200

NOCTARGET_X221_Y417_N200

UIB_R I0

NOCINITIATOR_X242_Y417_N202

NOCTARGET_X231_Y417_N200
I1

NOCINITIATOR_X258_Y417_N202

NOCTARGET_X237_Y417_N200

NOCTARGET_X242_Y417_N200
I2

NOCINITIATOR_X269_Y417_N202

NOCTARGET_X248_Y417_N200

NOCTARGET_X258_Y417_N200

NOCAXILITETARGET_X264_Y417_N200

NOCAXILITETARGET_X269_Y417_N200

NOCAXILITETARGET_X275_Y417_N200 (Visible in Chip Planner and Interface Planner but not user-accessible.)

GPIO-B_2 I0

NOCINITIATOR_X296_Y417_N202

NOCTARGET_X296_Y417_N200
I1

NOCINITIATOR_X311_Y417_N202

NOCAXILITETARGET_X311_Y417_N200
I2

NOCINITIATOR_X322_Y417_N202

NOCTARGET_X322_Y417_N200
GPIO-B/HPS I0 (fabric)

NOCINITIATOR_X357_Y417_N202

NOCTARGET_X346_Y417_N200
I1 (fabric)

NOCINITIATOR_X365_Y417_N202

NOCAXILITETARGET_X357_Y417_N200
I0 (MFFE)

AXI4 Lite T1 (MPFE)

I2 (MPFE)

NOCINITIATOR_X373_Y417_N202

NOCAXILITEINITIATOR_X373_Y417_N201

NOCINITIATOR_X373_Y417_N200

NOCTARGET_X365_Y417_N200
Table 11.  Bottom-Edge Hard Memory NoC Locations in Interface Planner
NoC Segment Initiator Interface Planner Location
PLL/SSM  

NOCPLL_X11_Y6_N221

NOCSSM_X11_Y6_N220

SDM I0

NOCINITIATOR_X28_Y6_N200

GPIO-B_0 I0

NOCINITIATOR_X79_Y6_N202

NOCTARGET_X79_Y6_N200

I1

NOCINITIATOR_X94_Y6_N202

NOCAXILITETARGET_X94_Y6_N200
I2 NOCINITIATOR_X105_Y6_N202

NOCTARGET_X105_Y6_N200

GPIO-B_1 I0

NOCINITIATOR_X134_Y6_N202

NOCTARGET_X134_Y6_N200
I1

NOCINITIATOR_X149_Y6_N202

NOCAXILITETARGET_X149_Y6_N200
I2

NOCINITIATOR_X160_Y6_N202

NOCTARGET_X160_Y6_N200
UIB_L I0

NOCINITIATOR_X188_Y6_N202

NOCAXILITETARGET_X177_Y6_N200 (Visible in Chip Planner and Interface Planner but not user-accessible.)

NOCAXILITETARGET_X183_Y6_N200

NOCAXILITETARGET_X188_Y6_N200

NOCTARGET_X194_Y6_N200

NOCTARGET_X204_Y6_N200

I1

NOCINITIATOR_X204_Y6_N202

NOCTARGET_X210_Y6_N200

NOCTARGET_X215_Y6_N200

I2

NOCINITIATOR_X215_Y6_N202

NOCTARGET_X221_Y6_N200

UIB_M I0

NOCINITIATOR_X242_Y6_N202

NOCTARGET_X231_Y6_N200

NOCTARGET_X237_Y6_N200

I1

NOCINITIATOR_X258_Y6_N202

NOCTARGET_X242_Y6_N200

NOCTARGET_X264_Y6_N200

I2

NOCINITIATOR_X269_Y6_N202

NOCTARGET_X269_Y6_N200

NOCTARGET_X275_Y6_N200

UIB_R I0

NOCINITIATOR_X296_Y6_N202

NOCTARGET_X285_Y6_N200

I1

NOCINITIATOR_X312_Y6_N202

NOCTARGET_X291_Y6_N200

NOCTARGET_X296_Y6_N200

I2

NOCINITIATOR_X323_Y6_N202

NOCTARGET_X302_Y6_N200

NOCTARGET_X312_Y6_N200

NOCAXILITETARGET_X318_Y6_N200

NOCAXILITETARGET_X323_Y6_N200

NOCAXILITETARGET_X329_Y6_N200 (Visible in Chip Planner and Interface Planner but not user-accessible.)

GPIO-B_2 I0

NOCINITIATOR_X350_Y6_N202

NOCTARGET_X350_Y6_N200
I1

NOCINITIATOR_X365_Y6_N202

NOCAXILITETARGET_X365_Y6_N200
I2

NOCINITIATOR_X376_Y6_N202

NOCTARGET_X376_Y6_N200
GPIO-B_3 I0

NOCINITIATOR_X404_Y6_N202

NOCTARGET_X404_Y6_N200
I1

NOCINITIATOR_X419_Y6_N202

NOCAXILITETARGET_X419_Y6_N200
I2

NOCINITIATOR_X430_Y6_N202

NOCTARGET_X430_Y6_N200
Level Two Title