Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 5/22/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel® Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel® Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. Fabric NoC 3.4. NoC Protocol Support 3.5. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.4. NoC Protocol Support x
3.4.1. AXI4 Protocol Support 3.4.2. AXI4 Handshaking Support 3.4.3. Quality of Service (QoS) Support 3.4.4. Transaction Ordering Support 3.4.5. AXI4 Lite Protocol Support
3.5. NoC Design Considerations x
3.5.1. Determining the Number of NoC Targets 3.5.2. Determining the Number of NoC Initiators 3.5.3. Fabric NoC Considerations 3.5.4. Latency Considerations 3.5.5. Initiator and Target Bandwidth Considerations 3.5.6. Horizontal Bandwidth Considerations 3.5.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. Options for Specifying NoC Connectivity and Addressing
4.3. NoC Building Blocks x
4.3.1. NoC Initiators 4.3.2. NoC Targets 4.3.3. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connecting NoC IP 4.4.3. NoC Initiator Connectivity Guidelines 4.4.4. NoC Target Connectivity Guidelines 4.4.5. NoC Clock Control Connectivity Guidelines
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.6. (Recommended) Make NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist 6.2. Generating a Simulation Registration Include File ( Intel® Quartus® Prime Compilation Flow) 6.3. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow) 6.4. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

4.6.4. NoC Performance Reports in Interface Planner

At any point during NoC initiator placement, you can interactively generate a NoC Performance Report in Interface Planner. The NoC Performance Report generation performs a static analysis of the NoC initiator and target locations to evaluate whether the placement allows your design to meet the bandwidth requirements and transaction sizes that you specify in the NoC Assignment Editor.

Note: The NoC Performance Report uses default clock frequencies when computing bandwidth capabilities. To generate a report based on actual clock frequencies, refer to the NoC Performance Report generated during the Fitter stage, as Fitter NoC Performance Reports describes.

To access the NoC Performance Report in Interface Planner, click the Reports tab, and then double-click Report NoC Performance in the Tasks pane.

Figure 25. Sample NoC Performance Report Not Meeting Performance Targets


The NoC Performance Report reports performance data for each initiator to target connection. The latencies in this report are based on the minimum structural latency with respect to the initiator and target placement. These latencies are for the NoC portion of the path only. These latencies do not include any latency of, for instance, external memory access. Nor do these latencies account for potential delay due to congestion on the NoC. You can achieve lower minimum structural latency by placing the NoC initiators and targets closer together.

Table 8.  NoC Performance Report Data
NoC Performance Report Column Description
Requested RD BW The requested read bandwidth in GB per second. This value is the same as the value that you specify in the NoC Assignment Editor, as Step 3: Make Attribute Assignments in the NoC Assignment Editor describes.
Requested WR BW The requested write bandwidth in GB per second. This value is the same as the value that you specify in the NoC Assignment Editor.
NoC Req latency The structural latency of the NOC request path between the initiator and target. This is the path used by read requests and write requests along with write data.
NoC Res latency The structural latency of the NOC response path between the target and initiator. This is the path used by read data and write acknowledgments returning to the initiator.
Initiator placement The placement location of the initiator element.
Target placement The placement location of the target element.
Message A message indicating whether you can achieve the requested bandwidth, or whether the connection is congested; and information about the cause of the congestion. The cause of congestion is an indication of where the congestion occurs, and which other connections contribute to that congestion.

One possible reason that the Message reports that the current placement cannot meet the requested bandwidth is because of over-saturation of an initiator or a target. For example, if the sum of all bandwidth requirements through a particular initiator is greater than the bandwidth that the initiator can support, based on the data width and operating frequency of its fabric facing AXI4 interface. To avoid this problem, either reduce bandwidth requirements or increase bandwidth capability.

Another possible reason that the current placement cannot meet the requested bandwidth is over-saturation of the horizontal bandwidth available in the NoC. This condition is the result of multiple initiator to target connections requesting bandwidth over the same sections of the horizontal links.

Further congestion can arise for connections that overlap connections that are already congested for any of the above reasons.

Note: For important considerations when choosing initiator interface bridge placement, refer to the tables in Horizontal Bandwidth Considerations, along with tables in Hard Memory NoC Locations in Interface Planner to translate location choices into physical placements.
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